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TMS320VC5507 датащи(PDF) 104 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 104 Page - Texas Instruments |
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104 / 108 page ![]() DP DN 5507 PU USBVDD CL CL D+ D U4 U3 R(PU) 1.5 k U5 U6 NOTES: A. A full-speed buffer is measured with the load shown. B. CL = 50 pF SM320VC5507-EP SPRS613 – SEPTEMBER 2009 www.ti.com Figure 5-40. Full-Speed Loads 5.18 ADC Timings Table 5-42 assumes testing over recommended operating conditions. Table 5-42. ADC Characteristics CVDD = 1.2 V CVDD = 1.6 V CVDD = 1.35 V NO. UNIT MIN MAX MIN MAX A1 tc(SCLC) Cycle time, ADC internal conversion clock 500 500 ns Delay time, ADC sample and hold acquisition A2 td(AQ) 40 40 μs time A3 td(CONV) Delay time, ADC conversion time 13 * tc(SCLC) 13 * tc(SCLC) ns Static differential non–linearity error 2 2 A4 SDNL LSB Static integral non–linearity error 3 3 A5 Zset Zero–scale offset error 9 9 LSB A6 Fset Full–scale offset error 9 9 LSB A7 Analog input impedance 1 1 MW 104 Electrical Specifications Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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