TMS320VC5507 datasheet(16/108 Pages) TI1

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SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

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Table 2-2. Signal Descriptions (continued)

TERMINAL

MULTIPLEXED

RESET

I/O/Z (1)

FUNCTION

BK (2)

NAME

SIGNAL NAME

CONDITION

EMIF chip select for memory space CE2 or HPI

control input 0. This pin serves in one of two

functions: EMIF chip-select for memory space

I/O/Z

CE2 (EMIF.CE2) or HPI control input 0

GPIO0 = 1:

(HPI.HCNTL0). The initial state of this pin

depends on the GPIO0 pin. See Section 3.6.1 for

Output,

more information.

EMIF.CE2

Active-low EMIF chip select for memory space

CE2. EMIF.CE2 is selected when the Parallel Port

EMIF.CE2

O/Z

Mode bit field of the External Bus Selection

GPIO0 = 0:

Input,

HPI control input 0. This pin, in conjunction with

HPI.HCNTL0

HPI.HCNTL1, selects a host access to one of the

HPI.HCNTL0

three HPI registers. HPI.HCNTL0 is selected when

the Parallel Port Mode bit field of the External Bus

Selection Register is set to 10 or 11.

EMIF chip select for memory space CE3,

general-purpose IO11, or HPI control input 1. This

pin serves in one of three functions: EMIF

chip-select for memory space CE3 (EMIF.CE3),

I/O/Z

general-purpose IO11 (GPIO11), or HPI control

input 1 (HPI.HCNTL1). The initial state of this pin

GPIO0 = 1:

depends on the GPIO0 pin. See Section 3.6.1 for

more information.

Output,

EMIF.CE3

Active-low EMIF chip select for memory space

CE3. EMIF.CE3 is selected when the Parallel Port

EMIF.CE3

O/Z

Mode bit field is of the External Bus Selection

GPIO0 = 0:

General-purpose IO11. GPIO11 is selected when

Input,

GPIO11

I/O/Z

the Parallel Port Mode bit field is set to 10.

HPI.HCNTL1

HPI control input 1. This pin, in conjunction with

HPI.HCNTL0, selects a host access to one of the

HPI.HCNTL1

three HPI registers. The HPI.HCNTL1 mode is

selected when the Parallel Port Mode bit field is

set to 11.

EMIF byte enable 0 control or HPI byte

identification. This pin serves in one of two

functions: EMIF byte enable 0 control (EMIF.BE0)

GPIO0 = 1:

I/O/Z

or HPI byte identification (HPI.HBE0). The initial

state of this pin depends on the GPIO0 pin. See

Output,

Section 3.6.1 for more information.

EMIF.BE0

Active-low EMIF byte enable 0 control. EMIF.BE0

is selected when the Parallel Port Mode bit field of

EMIF.BE0

O/Z

the External Bus Selection Register is set to 00 or

GPIO0 = 0:

01.

Input,

HPI byte identification. This pin, in conjunction

HPI.HBE0

with HPI.HBE1, identifies the first or second byte

HPI.HBE0

of the transfer. HPI.HBE0 is selected when the

Parallel Port Mode bit field is set to 10 or 11.

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