TMS320VC5507 datasheet(24/108 Pages) TI1

24 / 108 page

SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

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3.2

Memory

The 5507 supports a unified memory map (program and data accesses are made to the same physical

space). The total on-chip memory is 192K bytes (64K 16-bit words of RAM and 32K 16-bit words of ROM).

3.2.1

On-Chip Dual-Access RAM (DARAM)

The DARAM is located in the byte address range 000000h

−00FFFFh and is composed of eight blocks of

8K bytes each (see Table 3-1). Each DARAM block can perform two accesses per cycle (two reads, two

writes, or a read and a write). DARAM can be accessed by the internal program, data, or DMA buses. The

HPI can only access the first four (32K bytes) DARAM blocks.

Table 3-1. DARAM Blocks

BYTE ADDRESS RANGE

MEMORY BLOCK

000000h

− 001FFFh

DARAM 0 (HPI accessible)(1)

002000h

− 003FFFh

DARAM 1 (HPI accessible)

004000h

− 005FFFh

DARAM 2 (HPI accessible)

006000h

− 007FFFh

DARAM 3 (HPI accessible)

008000h

− 009FFFh

DARAM 4

00A000h

− 00BFFFh

DARAM 5

00C000h

− 00DFFFh

DARAM 6

00E000h

− 00FFFFh

DARAM 7

(1)

First 192 bytes are reserved for Memory-Mapped Registers (MMRs).

3.2.2

On-Chip Single-Access RAM (SARAM)

The SARAM is located at the byte address range 010000h

−01FFFFh and is composed of 8 blocks of 8K

bytes each (see Table 3-2). Each SARAM block can perform one access per cycle (one read or one

write). SARAM can be accessed by the internal program, data, or DMA buses.

Table 3-2. SARAM Blocks

BYTE ADDRESS RANGE

MEMORY BLOCK

010000h

− 011FFFh

SARAM 0

012000h

− 013FFFh

SARAM 1

014000h

− 015FFFh

SARAM 2

016000h

− 017FFFh

SARAM 3

018000h

− 019FFFh

SARAM 4

01A000h

− 01BFFFh

SARAM 5

01C000h

− 01DFFFh

SARAM 6

01E000h

− 01FFFFh

SARAM 7

3.2.3

On-Chip Read-Only Memory (ROM)

The one-wait-state ROM is located at the byte address range FF0000h

−FFFFFFh, for a total of 64K bytes

of ROM. The ROM address space can be mapped by software to the external memory or to the internal

ROM.

The standard 5507 device includes a bootloader program resident in the ROM. When the MPNMC bit field

of the ST3 status register is set through software, the on-chip ROM is disabled and not present in the

memory map, and byte address range FF0000h

−FFFFFFh is directed to external memory space. A

hardware reset always clears the MPNMC bit, so it is not possible to disable the ROM at reset. However,

the software reset instruction does not affect the MPNMC bit. The on-chip ROM can be accessed by the

program, data, or DMA buses. The first 16-bit word access to ROM requires three cycles. Subsequent

accesses require two cycles per 16-bit word.

Functional Overview

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