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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5507 датащи(PDF) 87 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 87 Page - Texas Instruments |
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87 / 108 page  SM320VC5507-EP www.ti.com SPRS613 – SEPTEMBER 2009 Table 5-25. McBSP1 and McBSP2 Timing Requirements (1) (continued) CVDD = 1.2 V CVDD = 1.6 V CVDD = 1.35 V NO. UNIT MIN MAX MIN MAX CLKR int -3 -3 Hold time, external FSR MC6 th (CKRL–FRH) ns high after CLKR low CLKR ext 1 1 CLKR int 11 7 Setup time, DR valid before MC7 tsu (DRV–CKRL) ns CLKR low CLKR ext 3 3 CLKR int -2 -2 Hold time, DR valid after MC8 th (CKRL–DRV) ns CLKR low CLKR ext 3 3 CLKX int 14 9 Setup time, external FSX MC9 tsu (FXH–CKXL) ns high before CLKX low CLKX ext 4 3 CLKX int -3 -3 Hold time, external FSX MC10 th (CKXL–FXH) ns high after CLKX low CLKX ext 1 1 Table 5-26. McBSP0 Switching Characteristics(1) (2) CVDD = 1.2 V CVDD = 1.6 V CVDD = 1.35 V NO. UNIT MIN MAX MIN MAX MC1 tc (CKRX) Cycle time, CLKR/X CLKR/X int 2P 2P ns MC3 tr (CKRX) Rise time, CLKR/X CLKR/X int 2 2 ns MC4 tf (CKRX) Fall time, CLKR/X CLKR/X int 2 2 ns MC11 tw (CKRXH) Pulse duration, CLKR/X high CLKR/X int D - 2(3) D + 2(3) D - 2(3) D + 2(3) ns MC12 tw (CKRXL) Pulse duration, CLKR/X low CLKR/X int C - 2(3) C + 2(3) C - 2(3) C + 2(3) ns CLKR int -3 2 -3 2 Delay time, CLKR high to internal FSR MC13 td (CKRH–FRV) ns valid CLKR ext 3 14 3 9 CLKX int -3 2 -3 2 Delay time, CLKX high to internal FSX MC14 td (CKXH–FXV) ns valid CLKX ext 4 15 4 9 CLKX int -3 3 -5 1 Disable time, DX high–impedance from MC15 tdis (CKXH–DXHZ) ns CLKX high following last data bit CLKX ext 10 19 3 12 Delay time, CLKX high to DX valid. This CLKX int 5 3 applies to all bits except the first bit CLKX ext 15 9 transmitted. CLKX int 4 2 Delay time, CLKX DXENA = 0 high to DX valid(4) CLKX ext 15 9 MC16 td (CKXH–DXV) ns Only applies to first bit CLKX int 2P + 1 2P + 1 transmitted when in Data Delay 1 or 2 DXENA = 1 CLKX ext 2P + 5 2P + 3 (XDATDLY=01b or 10b) modes (1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns. (3) T=CLKRX period = (1 + CLKGDV) * P C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even (4) See the TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA) and data delay features of the McBSP. Copyright © 2009, Texas Instruments Incorporated Electrical Specifications 87 Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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