TMS320VC5507 datasheet(39/108 Pages) TI1

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SM320VC5507-EP

www.ti.com

SPRS613 – SEPTEMBER 2009

Table 3-17. USB APLL Clock Mode Register Bit Functions

RESET

BIT NO.

BIT NAME

FUNCTION

VALUE

PLL Multiply Factor K. Multiply Factor K, combined with DIV and MODE, determines the final PLL

output clock frequency.

−12

MULT

K = MULT[3:0] + 1

PLL Divide Factor (D) selection bit for PLL multiply mode operation. DIV, combined with K and MODE,

determines the final PLL output clock frequency. When the PLL is operating in multiply mode:

DIV

DIV = 0;

PLL Divide Factor D = 1

DIV = 1;

PLL Divide Factor D = 2 if K is odd

PLL Divide Factor D = 4 if K is even

Status bit indicating if the APLL is the source for the USB module clock.8-bit counter for PLL lock

timer. When the MODE bit is set to 1, the COUNT field starts decrementing by 1 at the rate of

10-3

COUNT

CLKIN/16. When COUNT decrements to 0, the STAT bit is set to 1 and the PLL enabled clock is

sourced to the USB module.

PLL Voltage Controlled Oscillator (VCO) enable bit. This bit works in conjunction with MODE to enable

or disable the VCO.

MODE

VCO

OFF

X = Don’t care

PLL mode selection bit

MODE = 0;

PLL operating in divide mode (VCO bypassed). When the PLL is

operating in DIV mode, the PLL Divide Factor (D) is determined by the

factor K.

MODE

D = 2 if K = 1 to 15

D = 4 if K = 16

PLL operating in multiply mode (VCO on). The PLL multiply and divide

MODE = 1;

factors are determined by DIV and K.

PLL lock status bit

STAT

STAT = 0;

PLL operating in DIV mode (VCO bypassed)

STAT = 1;

PLL operating in multiply mode (VCO on)

DIV, combined with MODE and K, defines the final PLL multiplication ratio M/D as indicated below. The

USB APLL clock frequency can be simply expressed by Equation 1.

FUSB APLL CLK = FCLKIN x (M/D)

The multiplication factor M and the dividing factor D are defined in Table 3-18.

Table 3-18. M and D Values Based on MODE, DIV, and K

MODE

DIV

1 to 15

Odd

Even

K-1

Functional Overview

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