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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5507 датащи(PDF) 43 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 43 Page - Texas Instruments |
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43 / 108 page  SM320VC5507-EP www.ti.com SPRS613 – SEPTEMBER 2009 Table 3-22. DMA Configuration Registers PORT ADDRESS REGISTER NAME DESCRIPTION RESET VALUE (1) (WORD) GLOBAL REGISTER 0x0E00 DMA_GCR[2:0] DMA global control register xxxx xxxx xxxx x000 0x0E02 DMA_GSCR DMA software compatibility register 0x0E03 DMA_GTCR DMA timeout control register CHANNEL #0 REGISTERS 0x0C00 DMA_CSDP0 DMA channel 0 source destination parameters register 0000 0000 0000 0000 0x0C01 DMA_CCR0[15:0] DMA channel 0 control register 0000 0000 0000 0000 0x0C02 DMA_CICR0[5:0] DMA channel 0 interrupt control register xxxx xxxx xx00 0011 0x0C03 DMA_CSR0[6:0] DMA channel 0 status register xxxx xxxx xx00 0000 0x0C04 DMA_CSSA_L0 DMA channel 0 source start address register (lower bits) Undefined 0x0C05 DMA_CSSA_U0 DMA channel 0 source start address register (upper bits) Undefined DMA channel 0 source destination address register 0x0C06 DMA_CDSA_L0 Undefined (lower bits) DMA channel 0 Source destination address register (upper 0x0C07 DMA_CDSA_U0 Undefined bits) 0x0C08 DMA_CEN0 DMA channel 0 element number register Undefined 0x0C09 DMA_CFN0 DMA channel 0 frame number register Undefined 0x0C0A DMA_CSFI0 DMA channel 0 source frame index register Undefined 0x0C0B DMA_CSEI0 DMA channel 0 source element index register Undefined 0x0C0C DMA_CSAC0 DMA channel 0 source address counter Undefined 0x0C0D DMA_CDAC0 DMA channel 0 destination address counter Undefined 0x0C0E DMA_CDEI0 DMA channel 0 destination element index register Undefined 0x0C0F DMA_CDFI0 DMA channel 0 destination frame index register Undefined CHANNEL #1 REGISTERS 0x0C20 DMA_CSDP1 DMA channel 1 source destination parameters register 0000 0000 0000 0000 0x0C21 DMA_CCR1[15:0] DMA channel 1 control register 0000 0000 0000 0000 0x0C22 DMA_CICR1[5:0] DMA channel 1 interrupt control register xxxx xxxx xx00 0011 0x0C23 DMA_CSR1[6:0] DMA channel 1 status register xxxx xxxx xx00 0000 0x0C24 DMA_CSSA_L1 DMA channel 1 source start address register (lower bits) Undefined 0x0C25 DMA_CSSA_U1 DMA channel 1 source start address register (upper bits) Undefined DMA channel 1 source destination address register 0x0C26 DMA_CDSA_L1 Undefined (lower bits) DMA channel 1 source destination address register (upper 0x0C27 DMA_CDSA_U1 Undefined bits) 0x0C28 DMA_CEN1 DMA channel 1 element number register Undefined 0x0C29 DMA_CFN1 DMA channel 1 frame number register Undefined 0x0C2A DMA_CSFI1 DMA channel 1 source frame index register Undefined 0x0C2B DMA_CSEI1 DMA channel 1 source element index register Undefined 0x0C2C DMA_CSAC1 DMA channel 1 source address counter Undefined 0x0C2D DMA_CDAC1 DMA channel 1 destination address counter Undefined 0x0C2E DMA_CDEI1 DMA channel 1 destination element index register Undefined 0x0C2F DMA_CDFI1 DMA channel 1 destination frame index register Undefined CHANNEL #2 REGISTERS 0x0C40 DMA_CSDP2 DMA channel 2 source destination parameters register 0000 0000 0000 0000 0x0C41 DMA_CCR2[15:0] DMA channel 2 control register 0000 0000 0000 0000 0x0C42 DMA_CICR2[5:0] DMA channel 2 interrupt control register xxxx xxxx xx00 0011 (1) Hardware reset: x denotes a “don’t care.” Copyright © 2009, Texas Instruments Incorporated Functional Overview 43 Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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