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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5507 датащи(PDF) 54 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 54 Page - Texas Instruments |
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54 / 108 page  Reserved RTOS DLOG BERR R/W-00000 * R/W-0 R/W-0 R/W-0 7 6 5 4 3 2 1 0 I2C TINT1 DMAC3 DMAC2 INT4/RTC DMAC0 XINT0 INT1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R = Read, W = Write, n = value after reset * Always write zeros. SM320VC5507-EP SPRS613 – SEPTEMBER 2009 www.ti.com Table 3-37. IFR0 and IER0 Register Bit Fields (continued) 7 XINT1 This bit is used as the McBSP1 transmit interrupt flag/mask bit. 6 RINT1 McBSP1 receive interrupt flag/mask bit. 5 RINT0 McBSP0 receive interrupt flag bit 4 TINT0 Timer 0 interrupt flag bit 3 INT2 External interrupt 2 flag bit 2 INT0 External interrupt 0 flag bit 1-0 - Reserved for future expansion. These bits should always be written with 0. The IFR1 (Interrupt Flag Register 1) and IER1 (Interrupt Enable Register 1) bit layouts are shown in Figure 3-20. NOTE It is possible to have active interrupts simultaneously from both the external interrupt 4 (INT4) and the real-time clock (RTC). When an interrupt is detected in this bit, the real-time clock status register should be polled to determine if the real-time clock is the source of the interrupt. Figure 3-20. IFR1 and IER1 Bit Locations Table 3-38. IFR1 and IER1 Register Bit Fields BIT FUNCTION NUMBER NAME 15-11 - Reserved for future expansion. These bits should always be written with 0. 10 RTOS Real–time operating system interrupt flag/mask bit 9 DLOG Data log interrupt flag/mask bit 8 BERR Bus error interrupt flag/mask bit 7 I2C I2C interrupt flag/mask bit 6 TINT1 Timer 1 interrupt flag/mask bit 5 DMAC3 DMA channel 3 interrupt flag/mask bit 4 DMAC2 DMA channel 2 interrupt flag/mask bit This bit can be used as either the external user interrupt 4 flag/mask bit, or the real–time clock 3 INT4/RTC interrupt flag/mask bit. 2 DMAC0 DMA channel 0 interrupt flag/mask bit 1 XINT0 McBSP transmit 0 interrupt flag/mask bit 0 INT1 External user interrupt 1 flag/mask bit 54 Functional Overview Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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