TMS320VC5507 datasheet(4/108 Pages) TI1

4 / 108 page

SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

www.ti.com

List of Figures

2-1

144-Pin PGE Low-Profile Quad Flatpack (Top View)

....................................................................... 11

3-1

Block Diagram of the SM320VC5507

......................................................................................... 24

3-2

SM320VC5507 Memory Map

................................................................................................... 25

3-3

DMA_CCR Bit Locations

........................................................................................................ 27

3-4

External Bus Selection Register

................................................................................................ 29

3-5

Parallel Port Signal Routing

..................................................................................................... 33

3-6

Parallel Port (EMIF) Signal Interface

.......................................................................................... 33

3-7

I/O Direction Register (IODIR) Bit Layout

..................................................................................... 34

3-8

I/O Data Register (IODATA) Bit Layout

....................................................................................... 34

3-9

Address/GPIO Enable Register (AGPIOEN) Bit Layout

..................................................................... 35

3-10

Address/GPIO Direction Register (AGPIODIR) Bit Layout

................................................................. 35

3-11

Address/GPIO Data Register (AGPIODATA) Bit Layout

.................................................................... 35

3-12

EHPI GPIO Enable Register (EHPIGPIOEN) Bit Layout

.................................................................... 36

3-13

EHPI GPIO Direction Register (EHPIGPIODIR) Bit Layout

................................................................ 36

3-14

EHPI GPIO Data Register (EHPIGPIODATA) Bit Layout

................................................................... 37

3-15

System Register Bit Locations

.................................................................................................. 37

3-16

USB Clock Generation

........................................................................................................... 38

3-17

USB PLL Selection and Status Register Bit Layout

......................................................................... 38

3-18

USB APLL Clock Mode Register Bit Layout

.................................................................................. 39

3-19

IFR0 and IER0 Bit Locations

.................................................................................................... 53

3-20

IFR1 and IER1 Bit Locations

.................................................................................................... 54

4-1

Device Nomenclature for the TMS320VC5507

............................................................................... 57

5-1

3.3-V Test Load Circuit

.......................................................................................................... 65

5-2

Internal System Oscillator With External Crystal

............................................................................. 66

5-3

Bypass Mode Clock Timings

.................................................................................................... 68

5-4

External Multiply-by-N Clock Timings

.......................................................................................... 69

5-5

Real-Time Clock Oscillator With External Crystal

............................................................................ 70

5-6

Asynchronous Memory Read Timings

......................................................................................... 72

5-7

Asynchronous Memory Write Timings

......................................................................................... 72

5-8

Three SDRAM Read Commands

.............................................................................................. 74

5-9

Three SDRAM WRT Commands

............................................................................................... 75

5-10

SDRAM ACTV Command

....................................................................................................... 76

5-11

SDRAM DCAB Command

...................................................................................................... 77

5-12

SDRAM REFR Command

....................................................................................................... 78

5-13

SDRAM MRS Command

........................................................................................................ 79

5-14

SDRAM Self-Refresh Command

............................................................................................... 79

5-15

Power-Up Reset (On-Chip Oscillator Active) Timings

....................................................................... 80

5-16

Power-Up Reset (On-Chip Oscillator Inactive) Timings

..................................................................... 80

5-17

Reset Timings

.................................................................................................................... 81

5-18

External Interrupt Timings

....................................................................................................... 82

5-19

Wake-Up From IDLE Timings

.................................................................................................. 82

5-20

XF Timings

........................................................................................................................ 82

5-21

General-Purpose Input/Output (IOx) Signal Timings

........................................................................ 83

5-22

TIN/TOUT Timings When Configured as Inputs

............................................................................. 84

5-23

TIN/TOUT Timings When Configured as Outputs

........................................................................... 84

5-24

McBSP Receive Timings

........................................................................................................ 89

List of Figures

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