TMS320VC5507 datasheet(17/108 Pages) TI1

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SM320VC5507-EP

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SPRS613 – SEPTEMBER 2009

Table 2-2. Signal Descriptions (continued)

TERMINAL

MULTIPLEXED

RESET

I/O/Z (1)

FUNCTION

BK (2)

NAME

SIGNAL NAME

CONDITION

EMIF byte enable 1 control or HPI byte

identification. This pin serves in one of two

functions: EMIF byte enable 1 control (EMIF.BE1)

GPIO0 = 1:

I/O/Z

or HPI byte identification (HPI.HBE1). The initial

state of this pin depends on the GPIO0 pin. See

Output,

Section 3.6.1 for more information.

EMIF.BE1

Active-low EMIF byte enable 1 control. EMIF.BE1

is selected when the Parallel Port Mode bit field of

EMIF.BE1

O/Z

the External Bus Selection Register is set to 00 or

GPIO0 = 0:

01.

Input,

HPI byte identification. This pin, in conjunction

HPI.HBE1

with HPI.HBE0, identifies the first or second byte

HPI.HBE1

of the transfer. HPI.HBE1 is selected when the

Parallel Port Mode bit field is set to 10 or 11.

EMIF SDRAM row strobe, HPI address strobe, or

general-purpose IO12. This pin serves in one of

three functions: EMIF SDRAM row strobe

C10

I/O/Z

(EMIF.SDRAS), HPI address strobe (HPI.HAS), or

general-purpose IO12 (GPIO12). The initial state

GPIO0 = 1:

of this pin depends on the GPIO0 pin. See

Section 3.6.1 for more information.

Output,

EMIF.SDRAS

Active-low EMIF SDRAM row strobe.

EMIF.SDRAS is selected when the Parallel Port

EMIF.SDRAS

O/Z

Mode bit field of the External Bus Selection

GPIO0 = 0:

Active-low HPI address strobe. This signal latches

Input,

the address in the HPIA register in the HPI

HPI.HAS

Multiplexed mode. HPI.HAS is selected when the

Parallel Port Mode bit field is set to 11.

General-purpose IO12. GPIO12 is selected when

GPIO12

I/O/Z

the Parallel Port Mode bit field is set to 10.

EMIF SDRAM column strobe or HPI chip select

input. This pin serves in one of two functions:

EMIF SDRAM column strobe (EMIF.SDCAS) or

GPIO0 = 1:

C11

I/O/Z

HPI chip select input (HPI.HCS). The initial state

of this pin depends on the GPIO0 pin. See

Output,

Section 3.6.1 for more information.

EMIF.SDCAS

Active-low EMIF SDRAM column strobe.

EMIF.SDCAS is selected when the Parallel Port

EMIF.SDCAS

O/Z

Mode bit field of the External Bus Selection

GPIO0 = 0:

Input,

HPI Chip Select Input. HPI.HCS is the select input

HPI.HCS

for the HPI and must be driven low during

HPI.HCS

accesses. HPI.HCS is selected when the Parallel

Port Mode bit field is set to 10 or 11.

EMIF SDRAM write enable or HPI Data Strobe 1

input. This pin serves in one of two functions:

EMIF SDRAM write enable (EMIF.SDWE) or HPI

GPIO0 = 1:

C12

I/O/Z

data strobe 1 (HPI.HDS1). The initial state of this

pin depends on the GPIO0 pin. See Section 3.6.1

Output,

for more information.

EMIF.SDWE

EMIF SDRAM write enable. EMIF. SDWE is

selected when the Parallel Port Mode bit field of

EMIF.SDWE

O/Z

the External Bus Selection Register is set to 00 or

GPIO0 = 0:

01.

Input,

HPI Data Strobe 1 Input. HPI.HDS1 is driven by

HPI.HDS1

the host read or write strobes to control the

HPI.HDS1

transfer. HPI.HDS1 is selected when the Parallel

Port Mode bit field is set to 10 or 11.

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