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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5507 датащи(PDF) 53 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 53 Page - Texas Instruments |
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53 / 108 page  15 14 13 12 11 10 9 8 DMAC5 DMAC4 XINT2 RINT2 INT3/ WDTINT DSPINT DMAC1 USB R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 XINT1 RINT1 RINT0 TINT0 INT2 INT0 Reserved R/W R/W R/W R/W R/W R/W LEGEND: R = Read, W = Write, n = value after reset SM320VC5507-EP www.ti.com SPRS613 – SEPTEMBER 2009 Table 3-36. Interrupt Table (continued) INT4/RTC(3) SINT19 98 16 External interrupt #4 or RTC interrupt RINT2 SINT12 60 17 McBSP #2 receive interrupt XINT2 SINT13 68 18 McBSP #2 transmit interrupt DMAC2 SINT20 A0 19 DMA Channel #2 interrupt DMAC3 SINT21 A8 20 DMA Channel #3 interrupt DMAC4 SINT14 70 21 DMA Channel #4 interrupt DMAC5 SINT15 78 22 DMA Channel #5 interrupt TINT1 SINT22 B0 23 Timer #1 interrupt IIC SINT23 B8 24 I2C interrupt DLOG SINT25 C8 25 Data log interrupt RTOS SINT26 D0 26 Real–time operating system interrupt - SINT27 D8 27 Software interrupt #27 - SINT28 E0 28 Software interrupt #28 - SINT29 E8 29 Software interrupt #29 - SINT30 F0 30 Software interrupt #30 - SINT31 F8 31 Software interrupt #31 (3) It is recommended that either the INT4 or RTC interrupt be used. If both INT4 and RTC interrupts are used, one interrupt event can potentially hold off the other interrupt. For example, if INT4 is asserted first and held low, the RTC interrupt will not be recognized until the INT4 pin is back to high-logic state again. The INT4 pin must be pulled high if only the RTC interrupt is used. 3.12.1 IFR and IER Registers The IFR0 (Interrupt Flag Register 0) and IER0 (Interrupt Enable Register 0) bit layouts are shown in Figure 3-19. Figure 3-19. IFR0 and IER0 Bit Locations Table 3-37. IFR0 and IER0 Register Bit Fields BIT FUNCTION NUMBER NAME 15 DMAC5 DMA channel 5 interrupt flag/mask bit 14 DMAC4 DMA channel 4 interrupt flag/mask bit 13 XINT2 This bit is used as the McBSP2 transmit interrupt flag/mask bit. 12 RINT2 McBSP2 receive interrupt flag/mask bit. This bit is used as either the external user interrupt 3 flag/mask bit, or the watchdog timer interrupt 11 INT3/WDTINT flag/mask bit.(1) 10 DSPINT HPI host–to–DSP interrupt flag/mask. 9 DMAC1 DMA channel 1 interrupt flag/mask bit 8 USB USB interrupt flag/mask bit. (1) It is possible to have active interrupts simultaneously from both the external INT3 source and the watchdog timer. When an interrupt is detected in this bit, the watchdog timer status register should be polled to determine if the watchdog timer is the interrupt source. Copyright © 2009, Texas Instruments Incorporated Functional Overview 53 Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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