TMS320VC5507 datasheet(7/108 Pages) TI1

7 / 108 page

SM320VC5507-EP

www.ti.com

SPRS613 – SEPTEMBER 2009

5-7

Asynchronous Memory Cycle Timing Requirements

........................................................................ 70

5-8

Asynchronous Memory Cycle Switching Characteristics

.................................................................... 70

5-9

Synchronous DRAM Cycle Timing Requirements

........................................................................... 72

5-10

Synchronous DRAM Cycle Switching Characteristics

....................................................................... 72

5-11

Power-Up Reset (On-Chip Oscillator Active) Timing Requirements

....................................................... 79

5-12

Power-Up Reset (On-Chip Oscillator Inactive) Timing Requirements

..................................................... 80

5-13

Power-Up Reset (On-Chip Oscillator Inactive) Switching Characteristics

................................................ 80

5-14

Reset Timing Requirements

.................................................................................................... 80

5-15

Reset Switching Characteristics

............................................................................................... 81

5-16

External Interrupt Timing Requirements

...................................................................................... 81

5-17

Wake-Up From IDLE Switching Characteristics

............................................................................. 82

5-18

XF Switching Characteristics

................................................................................................... 82

5-19

GPIO Pins Configured as Inputs Timing Requirements

..................................................................... 83

5-20

GPIO Pins Configured as Outputs Switching Characteristics

.............................................................. 83

5-21

TIN/TOUT Pins Configured as Inputs Timing Requirements

.............................................................. 84

5-22

TIN/TOUT Pins Configured as Outputs Switching Characteristics

........................................................ 84

5-23

McBSP0 Timing Requirements

................................................................................................ 85

5-24

McBSP0 Switching Characteristics

........................................................................................... 85

5-25

McBSP1 and McBSP2 Timing Requirements

............................................................................... 86

5-26

McBSP0 Switching Characteristics

........................................................................................... 87

5-27

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)

................................. 89

5-28

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)

............................ 90

5-29

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)

................................. 91

5-30

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)

............................ 91

5-31

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)

................................. 92

5-32

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)

............................ 92

5-33

McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)

................................. 93

5-34

McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)

............................ 93

5-35

McBSP General-Purpose I/O Timing Requirements

......................................................................... 94

5-36

McBSP General-Purpose I/O Switching Characteristics

.................................................................... 94

5-37

EHPI Timing Requirements

..................................................................................................... 95

5-38

EHPI Switching Characteristics

................................................................................................ 95

5-39

2C Signals (SDA and SCL) Timing Requirements

......................................................................... 101

5-40

2C Signals (SDA and SCL) Timing Requirements

......................................................................... 102

5-41

Universal Serial Bus (USB) Characteristics

................................................................................. 103

5-42

ADC Characteristics

............................................................................................................ 104

6-1

Thermal Resistance Characteristics (Ambient)

............................................................................. 105

6-2

Thermal Resistance Characteristics (Case)

................................................................................. 105

List of Tables

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