TMS320VC5507 datasheet(65/108 Pages) TI1

65 / 108 page

Transmission Line

4.0 pF

1.85 pF

Z0 = 50

(see NOTE)

Tester Pin Electronics

Data Manual Timing Reference Point

Output

Under

Test

3.5 nH

Device Pin

(see NOTE)

SM320VC5507-EP

www.ti.com

SPRS613 – SEPTEMBER 2009

Figure 5-1. 3.3-V Test Load Circuit

5.4

ESD Performance

ESD stress levels were performed in compliance with the following JEDEC standards with the results indicated

below:

•

Charged Device Model (CDM), based on JEDEC Specification JESD22-C101, passed at ±500 V

•

Human Body Model (HBM), based on JEDEC Specification JESD22-A114, passed at ±1500 V

NOTE

According to industry research publications, ESD-CDM testing results show better correlation to

manufacturing line and field failure rates than ESD-HBM testing. 500-V CDM is commonly

considered as a safe passing level.

5.5

Timing Parameter Symbology

Timing parameter symbols used in the timing requirements and switching characteristics tables are created in

accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related

terminology have been abbreviated as follows:

Lowercase Subscripts and Their Meanings

Letters and Symbols and Their Meanings

access time

High

cycle time (period)

Low

delay time

Valid

dis

disable time

High-impedance

enable time

fall time

hold time

rise time

setup time

transition time

valid time

pulse duration (width)

unknown, changing or don't care level

Electrical Specifications

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