TMS320VC5507 datasheet(81/108 Pages) TI1

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RESET

BK Group †

High Group ‡

Z Group §

† BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, DX1, and DX2

‡ High group pins: C1[HPI.HINT], XF

§ Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSR0, CLKX0, DX0, FSX0, FSX2, CLKX2, FSR2, DR2, CLKR2,

FSX1, CLKX1, FSR1, DR1, CLKR1, A[20:16]

INTn

SM320VC5507-EP

www.ti.com

SPRS613 – SEPTEMBER 2009

Table 5-15. Reset Switching Characteristics(1)

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

td (RSTH–BKV)

Delay time, reset high to BK group valid(2)

38P + 15

td (RSTH–HIGHV)

Delay time, reset high to High group valid(3)

38P + 15

td (RSTL–ZIV)

Delay time, reset low to Z group invalid(4)

1P + 15

td (RSTH–ZV)

Delay time, reset high to Z group valid(4)

38P + 15

(1)

P = 1/CPU clock frequency in ns. For example, when CPU is running at 200 MHz, P = 5 ns.

(2)

BK group: Pins with bus keepers, holds previous state during reset. Following low-to-high transition of RESET, these pins go to their

post-reset logic state.

BK group pins: A’[0], A[15:0], D[15:0], C[14:2], C0, GPIO5, DX1, and DX2

(3)

High group: Following low-to-high transition of RESET, these pins go to logic-high state.

High group pins: C1[HPI.HINT], XF

(4)

Z group: Bidirectional pins which become input or output pins. Following low-to-high transition of RESET, these pins go to

high-impedance state.

Z group pins: C1[EMIF.AOE], GPIO[7:6, 4:0], TIN/TOUT0, SDA, SCL, CLKR0, FSR0, CLKX0, DX0, FSX0, FSX2, CLKX2, FSR2, DR2,

CLKR2, FSX1, CLKX1, FSR1, DR1, CLKR1, A[20:16]

Figure 5-17. Reset Timings

5.9

External Interrupt Timings

Table 5-16 assumes testing over recommended operating conditions (see Figure 5-18).

Table 5-16. External Interrupt Timing Requirements(1)

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

tw (INTH)A

Pulse width, interrupt high, CPU active

tw (INTL)A

Pulse width, interrupt low, CPU active

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

Figure 5-18. External Interrupt Timings

Electrical Specifications

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