TMS320VC5507 datasheet(34/108 Pages) TI1

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Reserved

IO7D

IO6D

IO5D

IO4D

IO3D

IO2D

IO1D

IO0D

R-00000000

R/W-pin

LEGEND: R = Read, W = Write, pin = value present on the pin (IO7-IO0 default to inputs after reset)

AIOEN15

AIOEN14

AIOEN13

AIOEN12

AIOEN11

AIOEN10

AIOEN9

AIOEN8

R/W, 0

AIOEN7

AIOEN6

AIOEN5

AIOEN4

AIOEN3

AIOEN2

AIOEN1

AIOEN0

R/W, 0

LEGEND: R = Read, W = Write, n = value after reset

SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

www.ti.com

Table 3-7. I/O Direction Register (IODIR) Bit Functions

RESET

BIT NO. BIT NAME

FUNCTION

VALUE

−8

Reserved

These bits are reserved and are unaffected by writes.

IOx Direction Control Bit. Controls whether IOx operates as an input or an output.

−0

IOxDIR

IOxDIR = 0;

IOx is configured as an input.

IOxDIR = 1;

IOx is configured as an output.

Figure 3-8. I/O Data Register (IODATA) Bit Layout

Table 3-8. I/O Data Register (IODATA) Bit Functions

RESET

BIT NO. BIT NAME

FUNCTION

VALUE

−8

Reserved

These bits are reserved and are unaffected by writes.

IOx Data Bit.

IOxD = 0;

The signal on the IOx pin is low.

IOxD = 1;

The signal on the IOx pin is high.

−0

IOxD

pin(1)

If IOx is configured as an output (IOxDIR = 1 in IODIR):

IOxD = 0;

Drive the signal on the IOx pin low.

IOxD = 1;

Drive the signal on the IOx pin high.

(1)

pin = value present on the pin (IO7

−IO0 default to inputs after reset)

3.7.2

Address Bus General-Purpose I/O

The 16 address signals, EMIF.A[15

−0], can also be individually enabled as GPIO when the Parallel Port

Mode bit field of the External Bus Selection Register is set for Data EMIF (00) or Multiplexed EHPI mode

(11). These pins are controlled by three registers: the enable register, AGPIOEN, determines if the pins

serve as GPIO or address (see Figure 3-9); the direction register, AGPIODIR, determines if the GPIO

enabled pin is an input or output (see Figure 3-10); and the data register, AGPIODATA, determines the

logic states of the pins in general-purpose I/O mode (see Figure 3-11).

Figure 3-9. Address/GPIO Enable Register (AGPIOEN) Bit Layout

Functional Overview

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