TMS320VC5507 datasheet(55/108 Pages) TI1

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SM320VC5507-EP

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SPRS613 – SEPTEMBER 2009

3.12.2 Interrupt Timing

The external interrupts (INT[4:0]) are synchronized to the CPU by way of a two-flip-flop synchronizer. The

interrupt inputs are sampled on falling edges of the CPU clock. A sequence of 1-1-0-0-0 on consecutive

cycles on the interrupt pin is required for an interrupt to be detected. Therefore, the minimum low pulse

duration on the external interrupts on the 5507 is three CPU clock periods.

3.12.3 Waking Up From IDLE Condition

One of the following four events can wake up the CPU from IDLE:

•

Hardware Reset

•

External Interrupt

•

RTC Interrupt

•

USB Event (Reset or Resume)

3.12.3.1 Waking Up From IDLE With Oscillator Disabled

With an external interrupt, a RTC interrupt, or an USB resume/reset, the clock generation circuit wakes up

the oscillator and enables the USB PLL to determine the oscillator stable time. In the case of the interrupt

being disabled by clearing the associated bit in the Interrupt Enable Register (IERx), the CPU is not

“woken up”. If the interrupt due to the wake-up event is enabled, the interrupt is sent to the CPU only after

the oscillator is stabilized and the USB PLL is locked. If the external interrupt serves as the wake-up

event, the interrupt line must stay low for a minimum of 3 CPU cycles after the oscillator is stabilized to

wake up the CPU. Otherwise, only the clock domain will wake up and another external interrupt will be

needed to wake up the CPU.

Once out of IDLE, any system not using the USB should put the USB module in idle mode to reduce

power consumption.

For more details on the SM320VC5507 oscillator-disable process, see the Disabling the Internal Oscillator

on the TMS320VC5507/5509/5509A DSP application report (literature number SPRA078).

3.12.4 Idling Clock Domain When External Parallel Bus Operating in EHPI Mode

The clock domain cannot be idled when the External Parallel Bus is operating in EHPI mode to ensure

host access to the DSP memory. To work around this restriction, use the HIDL bit of the External Bus

Selection Register (EBSR) with the CLKGENI bit of the Idle Control Register (ICR) to idle the clock

domain.

Functional Overview

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