TMS320VC5507 datasheet(86/108 Pages) TI1

86 / 108 page

SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

www.ti.com

Table 5-24. McBSP0 Switching Characteristics (1) (2) (continued)

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

Delay time, CLKX high to DX valid. This

CLKX int

applies to all bits except the first bit

CLKX ext

transmitted.

CLKX int

Delay time, CLKX

DXENA = 0

high to DX valid(4)

CLKX ext

MC16

td (CKXH–DXV)

Only applies to first bit

CLKX int

2P + 1

transmitted when in

Data Delay 1 or 2

DXENA = 1

CLKX ext

2P + 4

2P + 3

(XDATDLY = 01b or

10b) modes

Enable time, DX

CLKX int

-1

-3

driven from CLKX

DXENA = 0

CLKX ext

high(4)

Only applies to first bit

CLKX int

P - 1

P - 3

MC17

ten (CKXH–DX)

transmitted when in

Data Delay 1 or 2

DXENA = 1

CLKX ext

P + 6

P + 3

(XDATDLY= 01b or

10b) modes

FSX int

Delay time, FSX high

DXENA = 0

to DX valid(4)

FSX ext

Only applies to first bit

FSX int

2P + 1

MC18

td (FXH–DXV)

transmitted when in

Data Delay 0

DXENA = 1

FSX ext

2P + 10

(XDATDLY= 00b)

mode.

Enable time, DX

FSX int

driven from FSX

DXENA = 0

FSX ext

high(4)

Only applies to first bit

FSX int

P - 3

MC19

ten (FXH–DX)

transmitted when in

Data Delay 0

DXENA = 1

FSX ext

P + 8

P + 4

(XDATDLY= 00b)

mode

(4)

See the TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317) for a description of the DX enable

(DXENA) and data delay features of the McBSP.

5.14.2 McBSP1 and McBSP2 Timings

Table 5-25 and Table 5-26 assume testing over recommended operating conditions (see Figure 5-24 and

Figure 5-25).

Table 5-25. McBSP1 and McBSP2 Timing Requirements(1)

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

MC1

tc (CKRX)

Cycle time, CLKR/X

CLKR/X ext

2P(2)

Pulse duration, CLKR/X

MC2

tw (CKRX)

CLKR/X ext

P–1(2)

high or CLKR/X low

MC3

tr (CKRX)

Rise time, CLKR/X

CLKR/X ext

MC4

tf (CKRX)

Fall time, CLKR/X

CLKR/X ext

CLKR int

Setup time, external FSR

MC5

tsu (FRH–CKRL)

high before CLKR low

CLKR ext

(1)

Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that

signal are also inverted.

(2)

P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.

Electrical Specifications

Submit Documentation Feedback

Product Folder Link(s): SM320VC5507-EP

TMS320VC5507 датащи(PDF) 86 Page - Texas Instruments

TMS320VC5507 датащи(HTML) 86 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL