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TMS320VC5507 датащи(PDF) 96 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 96 Page - Texas Instruments |
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96 / 108 page ![]() HCNTL0 HR/W Read Data Valid HRDY HA[13:0] HDS HCS HD[15:0] (read) Valid E16 E14 E13 E1 E10 E2 Valid Valid Write Data HD[15:0] (write) E15 E17 E18 Read Write E6 E8 E7 E9 E13 E14 E15 HBE[1:0] Valid Valid NOTES: A. Any non-multiplexed access with HCNTL0 low will result in HPIC register access. For data read or write, HCNTL0 must stay high during the EHPI access. B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe, the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state. SM320VC5507-EP SPRS613 – SEPTEMBER 2009 www.ti.com Figure 5-32. EHPI Nonmultiplexed Read/Write Timings 96 Electrical Specifications Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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