TMS320VC5507 datasheet(67/108 Pages) TI1

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SM320VC5507-EP

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SPRS613 – SEPTEMBER 2009

practices should always be observed when planning trace routing to the discrete components used in the

oscillator circuit. Specifically, the crystal and the associated discrete components should be located as close to

the DSP as physically possible. Also, X1 and X2/CLKIN traces should be separated as soon as possible after

routing away from the DSP to minimize parasitic capacitance between them, and a ground trace should be run

between these two signal lines. This also helps to minimize stray capacitance between these two signals.

5.6.3

Clock Generation in Bypass Mode (DPLL Disabled)

The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of one, two, or four

to generate the internal CPU clock cycle. The divide factor (D) is set in the BYPASS_DIV field of the clock mode

the digital phase-locked loop (DPLL) clock synthesis is disabled.

Table 5-2 and Table 5-3 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5-3).

Table 5-2. CLKIN Timing Requirements

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

tc(CI)

Cycle time, X2/CLKIN

400(1)

tf(CI)

Fall time, X2/CLKIN

tr(CI)

Rise time, X2/CLKIN

C10

tw(CIL)

Pulse duration, CLKIN low

C11

tw(CIH)

Pulse duration, CLKIN high

(1)

This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. If an external crystal is used, the X2/CLKIN

cycle time is limited by the crystal frequency range listed in Table 5-1 .

Table 5-3. CLKOUT Switching Characteristics

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

D x tc(CI)

tc(CO)

Cycle time, CLKOUT

20(1)

D x tc(CI)

(2)

1600(3)

20(1)

1600(3)

(2)

Delay time, X2/CLKIN high to

td(CI–CO)

CLKOUT high/low

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H - 1

H + 1

H - 1

H + 1

tw(COH)

Pulse duration, CLKOUT high

H - 1

H + 1

H - 1

H + 1

(1)

It is recommended that the DPLL synthesized clocking option be used to obtain maximum operating frequency.

(2)

D = 1/(PLL Bypass Divider)

(3)

This device utilizes a fully static design and therefore can operate with tc(CO) approaching ∞. If an external crystal is used, the X2/CLKIN

cycle time is limited by the crystal frequency range listed in Table 5-1 .

Electrical Specifications

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