TMS320VC5507 datasheet(19/108 Pages) TI1

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SM320VC5507-EP

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SPRS613 – SEPTEMBER 2009

Table 2-2. Signal Descriptions (continued)

TERMINAL

MULTIPLEXED

RESET

I/O/Z (1)

FUNCTION

BK (2)

NAME

SIGNAL NAME

CONDITION

External flag. XF is set high by the BSET XF

instruction, set low by BCLR XF instruction or by

loading ST1. XF is used for signaling other

O/Z

processors in multiprocessor configurations or

Output

used as a general-purpose output pin. XF goes

into the high-impedance state when OFF is low,

and is set high following reset.

SDRAM CKE signal. The XF pin can be

configured to serve as SDRAM CKE pin by setting

Output

EMIF.CKE

O/Z

the following bits in the External Bus Selection

(XF)

default mode, this pin serves as XF.

OSCILLATOR/CLOCK SIGNALS

DSP clock output signal. CLKOUT cycles at the

CLKOUT

O/Z

machine-cycle rate of the CPU. CLKOUT goes

Output

into high-impedance state when OFF is low.

System clock/oscillator input. If the internal

oscillator is not being used, X2/CLKIN functions as

the clock input.

NOTE:

The USB module requires a 48-MHz clock.

Since this input clock is used by both the CPU

PLL and the USB module PLL, it must be a

Oscillator

X2/CLKIN

I/O

factor

MHz

order

for

the

Input

programmable PLL to produce the required

48-MHz

USB

module

clock.

In CLKGEN domain idle (OSC IDLE) mode,

this pin becomes output and is driven low to

stop external crystals (if used) from oscillating

or an external clock source from driving the

DSP’s internal logic.

Output pin from the internal system oscillator for

the crystal. If the internal oscillator is not used, X1

Oscillator

should be left unconnected. X1 does not go into

Output

the high-impedance state when OFF is low.

TIMER SIGNALS

Timer0 Input/Output. When output, TIN/TOUT0

signals a pulse or a change of state when the

on-chip timer counts down past zero. When input,

TIN/TOUT0 provides the clock source for the

internal timer module. At reset, this pin is

TIN/TOUT0

I/O/Z

Input

configured as an input.

NOTE:

Only the Timer0 signal is brought out. The

Timer1 signal is terminated internally and is

not available for external use.

REAL-TIME CLOCK

RTCINX1

Real-Time Clock Oscillator input

Input

RCINX2

Real-Time Clock Oscillator output

Output

I2C

I2C (bidirectional) data. At reset, this pin is in

SDA

I/O/Z

Hi-Z

high-impedance mode.

I2C (bidirectional) clock. At reset, this pin is in

SCL

I/O/Z

Hi-Z

high-impedance mode.

MULTICHANNEL BUFFERED SERIAL PORTS SIGNALS

McBSP0 receive clock. CLKR0 serves as the

CLKR0

I/O/Z

serial shift clock for the serial port receiver. At

Hi-Z

reset, this pin is in high-impedance mode.

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