TMS320VC5507 datasheet(72/108 Pages) TI1

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Setup = 2

Strobe = 5

Not Ready = 2

Hold = 1

Extended

Hold = 2

M17

CLKOUT †

CEx‡

BEx

A[20:0] §

D[15:0]

AOE

ARE

AWE

ARDY

M10

M18

M15

M16

† CLKOUT is equal to CPU clock

‡ CEx becomes active depending on the memory address space being accessed

§ A[13:0] for LQFP

SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

www.ti.com

Figure 5-7. Asynchronous Memory Write Timings

5.7.2

Synchronous DRAM (SDRAM) Timings

Table 5-9 and Table 5-10 assume testing over recommended operating conditions (see Figure 5-8 through

Figure 5-14).

Table 5-9. Synchronous DRAM Cycle Timing Requirements

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

M19

tsu (DV–CLKMEMH)

Setup time, read data valid before CLKMEM high

M20

th (CLKMEMH–DV)

Hold time, read data valid after CLKMEM high

M21

tc (CLKMEM)

Cycle time, CLKMEM

9.26(1)

7.52(2)

(1)

Maximum SDRAM operating frequency = 108 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC

board design and the memory chip timing requirement.

(2)

Maximum SDRAM operating frequency = 133 MHz. Actual attainable maximum operating frequency will depend on the quality of the PC

board design and the memory chip timing requirement.

Table 5-10. Synchronous DRAM Cycle Switching Characteristics

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

M22

td (CLKMEMH–CEL)

Delay time, CLKMEM high to CEx low

1.2

M23

td (CLKMEMH–CEH)

Delay time, CLKMEM high to CEx high

1.2

M24

td (CLKMEMH–BEV)

Delay time, CLKMEM high to BEx valid

1.2

Electrical Specifications

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