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TMS320VC5507 датащи(PDF) 99 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 99 Page - Texas Instruments |
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99 / 108 page ![]() HR/W Write Data Write Data n HRDY HCNTL[1:0] HDS HAS HCS HD[15:0] (write) HPIA contents Valid (01) Valid (01) n + 1 E11 E12 E15 E16 E20 E13 E17 E18 E9 E10 E10 E19 E14 E9 HBE[1:0] Valid Valid NOTES: A. During autoincrement mode, although the EHPI internally increments the memory address, reads of the HPIA register by the host will always indicate the base address. B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe, the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state. SM320VC5507-EP www.ti.com SPRS613 – SEPTEMBER 2009 Figure 5-35. EHPI Multiplexed Memory (HPID) Write Timings With Autoincrement Copyright © 2009, Texas Instruments Incorporated Electrical Specifications 99 Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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