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TMS320VC5507 датащи(PDF) 73 Page - Texas Instruments

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номер детали TMS320VC5507
подробное описание детали  Fixed-Point Digital Signal Processor
PDF  108 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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TMS320VC5507 датащи(HTML) 73 Page - Texas Instruments

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M22
M24
M26
M27
M23
M34
M28
M35
M29
M19
M20
D1
D2
D3
CLKMEM
CEx†
BEx ‡
EMIF.A[13:0]
D[15:0]
SDA10
SDRAS
SDCAS
SDWE
READ
READ
READ
CA1
CA2
CA3
M21
† The chip enable that becomes active depends on the address being accessed.
‡ All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals r emain
active until the next access that is not an SDRAM read occurs.
SM320VC5507-EP
www.ti.com
SPRS613 – SEPTEMBER 2009
Table 5-10. Synchronous DRAM Cycle Switching Characteristics (continued)
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
UNIT
MIN
MAX
MIN
MAX
M25
td (CLKMEMH–BEIV)
Delay time, CLKMEM high to BEx invalid
1.2
7
1.2
5
ns
M26
td (CLKMEMH–AV)
Delay time, CLKMEM high to address valid
1.2
7
1.2
5
ns
M27
td (CLKMEMH–AIV)
Delay time, CLKMEM high to address invalid
1.2
7
1.2
5
ns
M28
td (CLKMEMH–SDCASL)
Delay time, CLKMEM high to SDCAS low
1.2
7
1.2
5
ns
M29
td (CLKMEMH–SDCASH)
Delay time, CLKMEM high to SDCAS high
1.2
7
1.2
5
ns
M30
td (CLKMEMH–DV)
Delay time, CLKMEM high to data valid
1.2
7
1.2
5
ns
M31
td (CLKMEMH–DIV)
Delay time, CLKMEM high to data invalid
1.2
7
1.2
5
ns
M32
td (CLKMEMH–SDWEL)
Delay time, CLKMEM high to SDWE low
1.2
7
1.2
5
ns
M33
td (CLKMEMH–SDWEH)
Delay time, CLKMEM high to SDWE high
1.2
7
1.2
5
ns
M34
td (CLKMEMH–SDA10V)
Delay time, CLKMEM high to SDA10 valid
1.2
7
1.2
5
ns
M35
td (CLKMEMH–SDA10IV)
Delay time, CLKMEM high to SDA10 invalid
1.2
7
1.2
5
ns
M36
td (CLKMEMH–SDRASL)
Delay time, CLKMEM high to SDRAS low
1.2
7
1.2
5
ns
M37
td (CLKMEMH–SDRASH)
Delay time, CLKMEM high to SDRAS high
1.2
7
1.2
5
ns
M38
td (CLKMEMH–CKEL)
Delay time, CLKMEM high to CKE low
1.2
7
1.2
5
ns
M39
td (CLKMEMH–CKEH)
Delay time, CLKMEM high to CKE high
1.2
7
1.2
5
ns
Figure 5-8. Three SDRAM Read Commands
Copyright © 2009, Texas Instruments Incorporated
Electrical Specifications
73
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