TMS320VC5507 datasheet(20/108 Pages) TI1

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SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

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Table 2-2. Signal Descriptions (continued)

TERMINAL

MULTIPLEXED

RESET

I/O/Z (1)

FUNCTION

BK (2)

NAME

SIGNAL NAME

CONDITION

DR0

McBSP0 receive data

Input

McBSP0 receive frame synchronization. The

FSR0

I/O/Z

FSR0 pulse initiates the data receive process over

Hi-Z

DR0. At reset, this pin is in high-impedance mode.

McBSP0 transmit clock. CLKX0 serves as the

CLKX0

I/O/Z

serial shift clock for the serial port transmitter. The

Input

CLKX0 pin is configured as input after reset.

McBSP0 transmit data. DX0 is placed in the

DX0

O/Z

high-impedance state when not transmitting, when

Hi-Z

RESET is asserted, or when OFF is low.

McBSP0 transmit frame synchronization. The

FSX0

I/O/Z

FSX0 pulse initiates the data transmit process

Input

over DX0. Configured as an input following reset.

McBSP1 receive clock. CLKR1 serves as the

CLKR1

I/O/Z

Input

serial shift clock for the serial port receiver.

DR1

I/Z

McBSP1 serial data receive

Input

McBSP1 receive frame synchronization. The

FSR1

I/Z

FSR1 pulse initiates the data receive process over

Input

DR1.

McBSP1 serial data transmit. DX1 is placed in the

DX1

O/Z

high-impedance state when not transmitting, when

Hi-Z

RESET is asserted, or when OFF is low.

McBSP1 transmit clock. CLKX1 serves as the

CLKX1

I/O/Z

serial shift clock for the serial port transmitter. The

Input

CLKX1 pin is configured as input after reset.

McBSP2 receive clock. CLKR2 serves as the

CLKR2

I/O/Z

Input

serial shift clock for the serial port receiver.

DR2

McBSP2 serial data receive

Input

McBSP2 receive frame synchronization. The

FSR2

FSR2 pulse initiates the data receive process over

Input

DR2.

McBSP2 serial data transmit. DX2 is placed in the

DX2

O/Z

high-impedance state when not transmitting, when

Hi-Z

RESET is asserted, or when OFF is low.

McBSP2 transmit clock. CLKX2 serves as the

CLKX2

I/O/Z

serial shift clock for the serial port transmitter. The

Input

CLKX2 pin is configured as input after reset.

McBSP2 frame synchronization. The FSX2 pulse

FSX2

I/O/Z

initiates the data transmit process over DX2. FSX2

Input

is configured as an input following reset.

USB

Differential (positive) receive/transmit. At reset,

I/O/Z

Input

this pin is configured as input.

Differential (negative) receive/transmit. At reset,

I/O/Z

Input

this pin is configured as input.

Pullup output. This pin is used to pull up the

detection resistor required by the USB

O/Z

specification. The pin is internally connected to

Hi-Z

USBVDD via a software controllable switch

(CONN bit of the USBCTL register).

A/D

AIN0

Analog Input Channel 0

Input

AIN1

Analog Input Channel 1

Input

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