TMS320VC5507 datasheet(13/108 Pages) TI1

13 / 108 page

SM320VC5507-EP

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SPRS613 – SEPTEMBER 2009

2.3

Signal Descriptions

Table 2-2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for pin

locations.

Table 2-2. Signal Descriptions

TERMINAL

MULTIPLEXED

RESET

I/O/Z (1)

FUNCTION

BK (2)

NAME

SIGNAL NAME

CONDITION

PARALLEL BUS

A subset of the parallel address bus A13

−A0 of

the C55x DSP core bonded to external pins.

These pins serve in one of three functions: HPI

address bus (HPI.HA[13:0]), EMIF address bus

(EMIF.A[13:0]), or general-purpose I/O

(GPIO.A[13:0]). The initial state of these pins

depends on the GPIO0 pin. See Section 3.6.1 for

A[13:0]

I/O/Z

more information.

The address bus has a bus holder feature that

eliminates passive component requirement and

the power dissipation associated with them. The

bus holders keep the address bus at the previous

logic level when the bus goes into a

high-impedance state.

GPIO0 = 1:

HPI address bus. HPI.HA[13:0] is selected when

the Parallel Port Mode bit field of the External Bus

Output,

Selection Register is 10. This setting enables the

EMIF.A[13:0]

HPI in non-multiplexed mode.

HPI.HA[13:0]

HPI.HA[13:0] provides DSP internal memory

access to host. In non-multiplexed mode, these

GPIO0 = 0:

signals are driven by an external host as address

lines.

Input,

EMIF address bus. EMIF.A[13:0] is selected when

HPI.HA[13:0]

the Parallel Port Mode bit field of the External Bus

Selection Register is 01. This setting enables the

EMIF.A[13:0]

O/Z

full EMIF mode and the EMIF drives the parallel

port address bus. The internal A[14] address is

exclusive-ORed with internal A[0] address and the

result is routed to the A[0] pin.

General-purpose I/O address bus. GPIO.A[13:0] is

selected when the Parallel Port Mode bit field of

the External Bus Selection Register is 11. This

setting enables the HPI in multiplexed mode with

GPIO.A[13:0]

I/O/Z

the Parallel Port GPIO register controlling the

parallel port address bus. GPIO is also selected

when the Parallel Port Mode bit field is 00,

enabling the Data EMIF mode.

(1)

I = Input, O = Output, S = Supply, Hi-Z = High-impedance

(2)

BK = bus keeper (the bus keeper maintains the previous voltage level during reset or while the output pin is not driven), PU = pullup,

PD = pulldown, H = hysteresis input buffer, FS = fail-safe buffer

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