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TMS320VC5507 датащи(PDF) 78 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 78 Page - Texas Instruments |
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78 / 108 page ![]() M23 M37 M22 M36 CLKMEM CEx† BEx ‡ EMIF.A[13:0] D[15:0] SDA10 SDRAS SDCAS SDWE M32 M33 MRS MRS Value 0x30 § M26 M27 M28 M29 † The chip enable that becomes active depends on the address being accessed. ‡ All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain active until the next access that is not an SDRAM read occurs. § Write burst length = 1 Read latency = 3 Burst type = 0 (serial) Burst length = 1 SM320VC5507-EP SPRS613 – SEPTEMBER 2009 www.ti.com Figure 5-13. SDRAM MRS Command 78 Electrical Specifications Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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