TMS320VC5507 datasheet(63/108 Pages) TI1

63 / 108 page

SM320VC5507-EP

www.ti.com

SPRS613 – SEPTEMBER 2009

5.3.2

Electrical Characteristics Over Recommended Operating Case Temperature Range

for CVDD = 1.35 V (144 MHz) (Unless Otherwise Noted)

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

USBVDD = 3.0 V-3.6 V,

DN and DP(1)

2.8

USBVDD

IOH = -300 μA

USBVDD = 3.0 V-3.6 V,

0.9 x

VOH

High–level output voltage PU

USBVDD

IOH = -300 μA

USBVDD

DVDD = 2.7 V-3.6 V,

All other outputs

0.75 x DVDD

IOH = MAX

SDA & SCL(2)

At 3 mA sink current

0.4

VOL

Low–level output voltage

DN and DP(1)

IOL = 3.0 mA

0.3

All other outputs

IOL = MAX

0.4

Output–only or

DVDD = MAX,

I/O pins with bus

–300

300

VO = VSS to DVDD

keepers (enabled)

Input current for outputs

IIZ

μA

in high–impedance

All other

DVDD = MAX,

output–only or I/O

–5

VO = VSS to DVDD

pins

Input pins with

DVDD = MAX,

internal pulldown

300

VI = VSS to DVDD

(enabled)

Input pins with

DVDD = MAX,

internal pullup

–300

–30

VI = VSS to DVDD

Input current

μA

(enabled)

DVDD = MAX,

X2/CLKIN

–50

VI = VSS to DVDD

All other

DVDD = MAX,

–5

input–only pins

VI = VSS to DVDD

CVDD = 1.35 V,

CVDD Supply current, CPU + internal

IDDC

CPU clock = 144 MHz,

0.51

mA/MHz

memory access(3)

TC = 25°C

DVDD = 3.3 V,

IDDP

DVDD supply current, pins active

(4)

CPU clock = 144 MHz,

5.5

TC = 25°C

Oscillator

CVDD = 1.35 V,

CVDD supply current,

disabled. All

IDDC

TC = 25°C

125

μA

standby(5)

domains in

(Nominal process)

low–power state

Oscillator

DVDD = 3.3 V,

DVDD supply current,

disabled. All

IDDP

No I/O activity,

μA

standby

domains in

TC = 25°C

low–power state.

Input capacitance

Output capacitance

(1)

USB I/O pins DP and DN can tolerate a short circuit at D+ and D

− to 0 V or 5 V, as long as the recommended series resistors (see

Figure 5-40 ) are connected between the D+ and DP (package), and the D

− and DN (package). Do not apply a short circuit to the USB

I/O pins DP and DN in absence of the series resistors.

(2)

The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered

down.

(3)

CPU executing 75% Dual MAC + 25% ADD with moderate data bus activity (table of sine values). CPU and CLKGEN (DPLL) domain

are active. All other domains are idled.

(4)

One word of a table of a 16-bit sine value is written to the EMIF every 250 ns (64 Mbps). Each EMIF output pin is connected to a 10-pF

load.

(5)

In CLKGEN domain idle mode, X2/CLKIN becomes output and is driven low to stop external crystals (if used) from oscillating. Standby

current will be higher if an external clock source tries to drive the X2/CLKIN pin during this time.

Electrical Specifications

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