TMS320VC5507 datasheet(27/108 Pages) TI1

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DST AMODE

SRC AMODE

END PROG

Reserved

REPEAT

AUTO INIT

R/W, 00

R/W, 0

R, 0

R/W, 0

PRIO

SYNC

R/W, 0

R/W, 00000

LEGEND: R = Read, W = Write, n = value after reset

SM320VC5507-EP

www.ti.com

SPRS613 – SEPTEMBER 2009

•

USB full-speed slave interface supporting:

–

Bulk

–

Interrupt

–

Isochronous

•

I2C multi-master and slave interface (I2C compatible except, no fail-safe I/O buffers)

•

Real-time clock with crystal input, separate clock domain and supply pins

•

4-channel 10-bit Successive Approximation A/D

For detailed information on the C55x DSP peripherals, see the following documents:

•

TMS320C55x DSP Functional Overview (literature number SPRU312)

•

TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317)

3.4

Direct Memory Access (DMA) Controller

The 5507 DMA provides the following features:

•

Four standard ports, one for each of the following data resources: DARAM, SARAM, peripherals and

external memory

•

Six channels, which allow the DMA controller to track the context of six independent DMA channels

•

Programmable low/high priority for each DMA channel

•

One interrupt for each DMA channel

•

Event synchronization. DMA transfers in each channel can be dependent on the occurrence of

selected events.

•

Programmable address modification for source and destination addresses

•

Dedicated idle domain allows the DMA controller to be placed in a low-power (idle) state under

software control.

•

Dedicated DMA channel used by the HPI to access internal memory (DARAM)

The 5507 DMA controller allows transfers to be synchronized to selected events. The 5507 supports 15

separate sync events and each channel can be tied to separate sync events independent of the other

channels. Sync events are selected by programming the SYNC field in the channel-specific DMA channel

control register (DMA_CCR).

3.4.1

DMA Channel Control Register (DMA_CCR)

The channel control register (DMA_CCR) bit layouts are shown in Figure 3-3.

Figure 3-3. DMA_CCR Bit Locations

The SYNC[4:0] bits specify the event that can initiate the DMA transfer for the corresponding DMA

channel. The five bits allow several configurations as listed in Table 3-4. The bits are set to zero upon

reset. For those synchronization modes with more than one peripheral listed, the Serial Port Mode bit field

of the External Bus Selection Register dictates which peripheral event is actually connected to the DMA

input.

Functional Overview

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