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TMS320VC5507 датащи(PDF) 102 Page - Texas Instruments

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номер детали TMS320VC5507
подробное описание детали  Fixed-Point Digital Signal Processor
PDF  108 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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TMS320VC5507 датащи(HTML) 102 Page - Texas Instruments

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IC10
IC8
IC4
IC3
IC7
IC12
IC5
IC6
IC14
IC2
IC3
IC13
Stop
Start
Repeated
Start
Stop
SDA
SCL
IC1
IC11
IC9
SM320VC5507-EP
SPRS613 – SEPTEMBER 2009
www.ti.com
Figure 5-37. I2C Receive Timings
Table 5-40. I2C Signals (SDA and SCL) Timing Requirements
CVDD = 1.2 V
CVDD = 1.6 V
CVDD = 1.35 V
NO.
STANDARD
FAST
STANDARD
FAST
UNIT
MODE
MODE
MODE
MODE
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
IC16
tc(SCL)
Cycle time, SCL
10
2.5
10
2.5
μs
Delay time, SCL high to
IC17
td(SCLH–SDAL)
SDA low for a repeated
4.7
0.6
4.7
0.6
μs
START condition
Delay time, SDA low to
SCL low for a START and
IC18
td(SDAL–SCLL)
4
0.6
4
0.6
μs
a repeated START
condition
IC19
tw(SCLL)
Pulse duration, SCL low
4.7
1.3
4.7
1.3
μs
IC20
tw(SCLH)
Pulse duration, SCL high
4
0.6
4
0.6
μs
Delay time, SDA valid to
IC21
td(SDA–SCLH)
250
100
250
100
ns
SCL high
Valid time, SDA valid after
IC22
tv(SCLL–SDAV)
0
0
0.9
0
0
0.9
μs
SCL low
Pulse duration, SDA high
IC23
tw(SDAH)
between STOP and
4.7
1.3
4.7
1.3
μs
START conditions
20 +
20 +
IC24
tr(SDA)
Rise time, SDA
1000
300
1000
0.1Cb
300
ns
0.1Cb
(1)
(1)
20 +
20 +
IC25
tr(SCL)
Rise time, SCL
1000
300
1000
0.1Cb
300
ns
0.1Cb
(1)
(1)
20 +
20 +
IC26
tf(SDA)
Fall time, SDA
300
300
300
0.1Cb
300
ns
0.1Cb
(1)
(1)
20 +
20 +
IC27
tf(SCL)
Fall time, SCL
300
300
300
0.1Cb
300
ns
0.1Cb
(1)
(1)
Delay time, SCL high to
IC28
td(SCLH–SDAH)
SDA high for a STOP
4
0.6
4
0.6
μs
condition
Capacitance for each
IC29
Cp
10
10
10
10
pF
I2C pin
(1)
Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
102
Electrical Specifications
Copyright © 2009, Texas Instruments Incorporated
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