TMS320VC5507 datasheet(82/108 Pages) TI1

82 / 108 page

CLKOUT †

† CLKOUT reflects the CPU clock.

SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

www.ti.com

5.10 Wake-Up From IDLE

(2)assumes testing over recommended operating conditions (see Figure 5-19).

Table 5-17. Wake-Up From IDLE Switching Characteristics(1)

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

TYP

MAX

MIN

TYP

MAX

Delay time, wake–up event low to clock

ID1

td (WKPEVTL–CLKGEN)

generation enable

1.25(2)

(CPU and clock domain idle)

Hold time, clock generation enable to wake–up

ID2

th (CLKGEN–WKPEVTL)

event low

3P(3)

(CPU and clock domain in idle)

Pulse width, wake–up event low

ID3

tw (WKPEVTL)

(for CPU idle only)

(2)

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

(2)

Estimated data based on 12-MHz crystal used with on-chip oscillator at 25°C. This number will vary based on the actual crystal

characteristics operating condition and the PC board layout and the parasitics.

(3)

Following the clock generation domain idle, the INTx becomes level-sensitive and stays that way until the low-to-high transition of INTx

following the CPU wake-up. Holding the INTx low longer than minimum requirement will send more than one interrupt to the CPU. The

number of interrupts sent to the CPU depends on the INTx-low time following the CPU wake-up from IDLE.

Figure 5-19. Wake-Up From IDLE Timings

5.11 XF Timings

Table 5-18 assumes testing over recommended operating conditions (see Figure 5-20).

Table 5-18. XF Switching Characteristics

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

Delay time, CLKOUT high to XF high

–1

td (XF)

Delay time, CLKOUT high to XF low

–1

Figure 5-20. XF Timings

Electrical Specifications

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