TMS320VC5507 datasheet(80/108 Pages) TI1

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CVDD

DVDD

CLKOUT

X2/CLKIN

RESET

SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

www.ti.com

5.8.2

Power-Up Reset (On-Chip Oscillator Inactive)

Table 5-12 and Table 5-13 assume testing over recommended operating conditions (see Figure 5-16).

Table 5-12. Power-Up Reset (On-Chip Oscillator Inactive) Timing Requirements

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

th (CLKOUTV-RSTL)

Hold time, CLKOUT valid to RESET low

3P(1)

(1)

P = 1/(input clock frequency) in ns. For example, when input clock is 12 MHz, P = 83.33 ns.

Table 5-13. Power-Up Reset (On-Chip Oscillator Inactive) Switching Characteristics

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

td (CLKINV-CLKOUTV) Delay time, CLKIN valid to CLKOUT valid

Figure 5-16. Power-Up Reset (On-Chip Oscillator Inactive) Timings

5.8.3

Warm Reset

Table 5-14 and Table 5-15 assume testing over recommended operating conditions (see Figure 5-17).

Table 5-14. Reset Timing Requirements

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

tw (RSL)

Pulse width, reset low

3P(1)

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

Electrical Specifications

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