TMS320VC5507 datasheet(68/108 Pages) TI1

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X2/CLKIN

CLKOUT

C10

C11

NOTE A: The relationship of X2/CLKIN to CLKOUT depends on the PLL bypass divide factor chosen for the CLKMD register. The wavefo rm

relationship shown in Figure 53 is intendedtoillustratethetimingparametersbasedonCLKOUT =1/2(CLKIN)configuration.

−

SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

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Figure 5-3. Bypass Mode Clock Timings

5.6.4

Clock Generation in Lock Mode (DPLL Synthesis Enabled)

The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a synthesis factor of N to

generate the internal CPU clock cycle. The synthesis factor is determined by:

(3)

Where:

1. M = the multiply factor set in the PLL_MULT field of the clock mode register

2. DL = the divide factor set in the PLL_DIV field of the clock mode register

Valid values for M are (multiply by) 2 to 31. Valid values for DL are (divide by) 1, 2, 3, and 4.

For detailed information on clock generation configuration, see the TMS320C55x DSP Peripherals Overview

Reference Guide (literature number SPRU317).

Table 5-4 and Table 5-5 assume testing over recommended operating conditions and H = 0.5tc(CO) (see

Figure 5-4).

Table 5-4. CLKIN Timing Requirements

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

tc(CI)

Cycle time, X2/CLKIN

DPLL synthesis enabled

20(1)

400

20(1)

400

tf(CI)

Fall time, X2/CLKIN

tr(CI)

Rise time, X2/CLKIN

C10

tw(CIL)

Pulse duration, CLKIN low

C11

tw(CIH)

Pulse duration, CLKIN high

(1)

This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. If an external crystal is used, the X2/CLKIN

cycle time is limited by the crystal frequency range listed in Table 5-1 .

Electrical Specifications

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