TMS320VC5507 datasheet(95/108 Pages) TI1

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E21

CLKOUT †

HINT

† CLKOUT reflects the CPU clock.

SM320VC5507-EP

www.ti.com

SPRS613 – SEPTEMBER 2009

5.15 Enhanced Host-Port Interface (EHPI) Timings

Table 5-37 and Table 5-38 assume testing over recommended operating conditions (see Figure 5-31 through

Figure 5-36).

Table 5-37. EHPI Timing Requirements

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

E11

tsu (HASL–HDSL)

Setup time, HAS low before HDS low

E12

th (HDSL–HASL)

Hold time, HAS low after HDS low

Setup time, (HR/W, HA[13:0], HBE [1:0], HCNTL[1:0]) valid

E13

tsu (HCNTLV–HDSL)

before HDS low

Hold time, (HR/W, HA[13:0], HBE [1:0], HCNTL[1:0]) invalid

E14

th (HDSL–HCNTLIV)

after HDS low

E15

tw (HDSL)

Pulse duration, HDS low

4P(1)

E16

tw (HDSH)

Pulse duration, HDS high

4P(1)

E17

tsu (HDV–HDSH)

Setup time, HD bus write data valid before HDS high

E18

th (HDSH–HDIV)

Hold time, HD bus write data invalid after HDS high

Setup time, (HR/W, HBE [1:0], HCNTL[1:0]) valid before

E19

tsu (HCNTLV–HASL)

HAS low

Hold time, (HR/W, HBE [1:0], HCNTL[1:0]) valid after HAS

E20

th (HASL–HCNTLIV)

low

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

Table 5-38. EHPI Switching Characteristics

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

ten (HDSL–HDD)M

Enable time, HDS low to HD bus enabled (memory access)

Delay time, HDS low to HD bus read data valid

td (HDSL–HDV)M

14P(1) (2)

(memory access)

ten (HDSL–HDD)R

Enable time, HDS low to HD enabled (register access)

Delay time, HDS low to HD bus read data valid

td (HDSL–HDV)R

(register access)

tdis (HDSH–HDIV)

Disable time, HDS high to HD bus read data invalid

td (HDSL–HRDYL)

Delay time, HDS low to HRDY low (during reads)

td (HDV–HRDYH)

Delay time, HD bus valid to HRDY high (during reads)

td (HDSH–HRDYL)

Delay time, HDS high to HRDY low (during writes)

E10

td (HDSH–HRDYH)

Delay time, HDS high to HRDY high (during writes)

14P(1) (2)

E21

td (COH–HINT)

Delay time, CLKOUT high to HINT high/low

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

(2)

EHPI latency is dependent on the number of DMA channels active, their priorities and their source/destination ports. The latency shown

assumes no competing CPU or DMA activity to the memory resource being accessed by the EHPI.

Figure 5-31. HINT Timings

Electrical Specifications

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