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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5507 датащи(PDF) 85 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 85 Page - Texas Instruments |
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85 / 108 page  SM320VC5507-EP www.ti.com SPRS613 – SEPTEMBER 2009 5.14 Multichannel Buffered Serial Port (McBSP) Timings 5.14.1 McBSP0 Timings Table 5-23 and Table 5-24 assume testing over recommended operating conditions (see Figure 5-24 and Figure 5-25). Table 5-23. McBSP0 Timing Requirements(1) CVDD = 1.2 V CVDD = 1.6 V CVDD = 1.35 V NO. UNIT MIN MAX MIN MAX MC1 tc (CKRX) Cycle time, CLKR/X CLKR/X ext 2P(2) 2P(2) ns Pulse duration, CLKR/X MC2 tw (CKRX) CLKR/X ext P–1(2) P–1(2) ns high or CLKR/X low MC3 tr (CKRX) Rise time, CLKR/X CLKR/X ext 6 6 ns MC4 tf (CKRX) Fall time, CLKR/X CLKR/X ext 6 6 ns CLKR int 10 7 Setup time, external FSR MC5 tsu (FRH–CKRL) ns high before CLKR low CLKR ext 2 2 CLKR int -3 -3 Hold time, external FSR MC6 th (CKRL–FRH) ns high after CLKR low CLKR ext 1 1 CLKR int 10 7 Setup time, DR valid before MC7 tsu (DRV–CKRL) ns CLKR low CLKR ext 2 2 CLKR int -2 -2 Hold time, DR valid after MC8 th (CKRL–DRV) ns CLKR low CLKR ext 3 3 CLKX int 13 8 Setup time, external FSX MC9 tsu (FXH–CKXL) ns high before CLKX low CLKX ext 3 2 CLKX int -3 -3 Hold time, external FSX MC10 th (CKXL–FXH) ns high after CLKX low CLKX ext 1 1 (1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns. Table 5-24. McBSP0 Switching Characteristics(1) (2) CVDD = 1.2 V CVDD = 1.6 V CVDD = 1.35 V NO. UNIT MIN MAX MIN MAX MC1 tc (CKRX) Cycle time, CLKR/X CLKR/X int 2P 2P ns MC3 tr (CKRX) Rise time, CLKR/X CLKR/X int 1 1 ns MC4 tf (CKRX) Fall time, CLKR/X CLKR/X int 1 1 ns MC11 tw (CKRXH) Pulse duration, CLKR/X high CLKR/X int D-2(3) D+2(3) D-1(3) D+1(3) ns MC12 tw (CKRXL) Pulse duration, CLKR/X low CLKR/X int C-2(3) C+2(3) C-1(3) C+1(3) ns CLKR int -2 1 -2 1 Delay time, CLKR high to internal FSR MC13 td (CKRH–FRV) ns valid CLKR ext 4 13 4 8 CLKX int -2 2 -2 2 Delay time, CLKX high to internal FSX MC14 td (CKXH–FXV) ns valid CLKX ext 4 15 4 9 CLKX int 0 5 -5 1 Disable time, DX high–impedance from MC15 tdis (CKXH–DXHZ) ns CLKX high following last data bit CLKX ext 10 18 3 11 (1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are also inverted. (2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns. (3) T=CLKRX period = (1 + CLKGDV) * P C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even Copyright © 2009, Texas Instruments Incorporated Electrical Specifications 85 Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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