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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5507 датащи(PDF) 50 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 50 Page - Texas Instruments |
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50 / 108 page  SM320VC5507-EP SPRS613 – SEPTEMBER 2009 www.ti.com Table 3-31. I2C Module Registers (1) (continued) 0x3C00 I2COAR[9:0](3) I2C own address register 0000 0000 0000 0000 0x3C01 I2CIER I2C interrupt enable register 0000 0000 0000 0000 0x3C02 I2CSTR I2C status register 0000 0001 0000 0000 0x3C03 I2CCLKL[15:0] I2C clock divider low register 0000 0000 0000 0000 0x3C04 I2CCLKH[15:0] I2C clock divider high register 0000 0000 0000 0000 0x3C05 I2CCNT[15:0] I2C data count 0000 0000 0000 0000 0x3C06 I2CDRR[7:0] I2C data receive register 0000 0000 0000 0000 0x3C07 I2CSAR[9:0] I2C slave address register 0000 0011 1111 1111 0x3C08 I2CDXR[7:0] I2C data transmit register 0000 0000 0000 0000 0x3C09 I2CMDR[14:0] I2C mode register 0000 0000 0000 0000 0x3C0A I2CISRC I2C interrupt source register 0000 0000 0000 0000 0x3C0B - Reserved 0x3C0C I2CPSC I2C prescaler register 0000 0000 0000 0000 0x3C0D - Reserved 0x3C0E - Reserved 0x3C0F I2CMDR2 I2C mode register 2 0000 0000 0000 0000 - I2CRSR I2C receive shift register (not accessible to the CPU) - I2CXSR I2C transmit shift register (not accessible to the CPU) (3) This register must be set by the user. The user may program the I2C’s own address to any value, as long as the value does not conflict with the I2C addresses of other components connected to the I2C bus. Table 3-32. Watchdog Timer Registers WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE (1) 0x4000 WDTIM[15:0] WD timer counter register 1111 1111 1111 1111 0x4001 WDPRD[15:0] WD timer period register 1111 1111 1111 1111 0x4002 WDTCR[13:0] WD timer control register 0000 0011 1100 1111 0x4003 WDTCR2[15:0] WD timer control register 2 0001 0000 0000 0000 (1) Hardware reset; x denotes a “don’t care.” Table 3-33. USB Module Registers WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE(1) (2) DMA CONTEXTS 0x5800 Reserved 0x5808 DMAC_O1 Output endpoint 1 DMA context register Undefined 0x5810 DMAC_O2 Output endpoint 2 DMA context register Undefined 0x5818 DMAC_O3 Output endpoint 3 DMA context register Undefined 0x5820 DMAC_O4 Output endpoint 4 DMA context register Undefined 0x5828 DMAC_O5 Output endpoint 5 DMA context register Undefined 0x5830 DMAC_O6 Output endpoint 6 DMA context register Undefined 0x5838 DMAC_O7 Output endpoint 7 DMA context register Undefined 0x5840 Reserved 0x5848 DMAC_I1 Input endpoint 1 DMA context register Undefined 0x5850 DMAC_I2 Input endpoint 2 DMA context register Undefined 0x5858 DMAC_I3 Input endpoint 3 DMA context register Undefined 0x5860 DMAC_I4 Input endpoint 4 DMA context register Undefined (1) Hardware reset; x denotes a “don’t care.” (2) The USB module must be brought out of reset by setting bit 2 of the USB Idle Control and Status Register before any USB module register read or write attempt. 50 Functional Overview Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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