TMS320VC5507 datasheet(93/108 Pages) TI1

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LSB

MC26

MC29

MC23

MC24

MSB

CLKX

FSX

Bit (n1)

(n2)

(n3)

(n4)

Bit 0

Bit (n1)

(n2)

(n3)

(n4)

MC37

MC39

MC36

MC38

MC32

SM320VC5507-EP

www.ti.com

SPRS613 – SEPTEMBER 2009

Table 5-33. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)(1) (2)

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MASTER

SLAVE

MASTER

SLAVE

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MC23

tsu (DRV–CKXL)

Setup time, DR valid before CLKX low

3 - 6P

MC24

th (CKXL–DRV)

Hold time, DR valid after CLKX low

3 + 6P

MC36

tsu (FXL–CKXL)

Setup time, FSX low before CLKX low

MC26

tc (CKX)

Cycle time, CLKX

16P

(1)

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)

P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.

Table 5-34. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)(1) (2)

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MASTER (3)

SLAVE

MASTER (3)

SLAVE

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Delay time, CLKX high to FSX

MC37 td(CKXH–FXL)

D - 5

D + 5

D - 4

D + 4

low(4)

Delay time, FSX low to CLKX

MC38 td(FXL–CKXL)

T - 5

T + 5

T - 4

T + 4

low(5)

Delay time, CLKX high to DX

MC29 td(CKXH–DXV)

-4

6 3P + 3

5P + 15

-3

3 3P + 3

5P + 8

valid

Disable time, DX

MC39 tdis(CKXH–DXHZ)

high–impedance following last

-4

4 3P + 4

3P + 19

-3

1 3P + 3

3P + 12

data bit from CLKX high

MC32 td(FXL–DXV)

Delay time, FSX low to DX valid

C - 4

C + 4 3P + 4

3P + 18

C - 3

C + 3 3P + 4

3P + 10

(1)

For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

(2)

P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.

(3)

T = CLKX period = (1 + CLKGDV) * 2P

C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even

(4)

FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on

FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP

(5)

FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master

clock (CLKX).

Figure 5-29. McBSP Timings as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

Electrical Specifications

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