TMS320VC5507 datasheet(84/108 Pages) TI1

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TIN/TOUT

as Input

TIN/TOUT

as Output

CLKOUT

SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

www.ti.com

5.13 TIN/TOUT Timings (Timer0 Only)

Table 5-21 and Table 5-22 assume testing over recommended operating conditions (see Figure 5-22 and

Figure 5-23).

Table 5-21. TIN/TOUT Pins Configured as Inputs Timing Requirements(1) (2)

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

tw (TIN/TOUTL)

Pulse width, TIN/TOUT low

2P + 1

tw (TIN/TOUTH)

Pulse width, TIN/TOUT high

2P + 1

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

(2)

Only the Timer0 signal is externally available. The Timer1 signal is internally terminated and is not available for external use.

Table 5-22. TIN/TOUT Pins Configured as Outputs Switching Characteristics(1) (2) (3)

CVDD = 1.2 V

CVDD = 1.6 V

CVDD = 1.35 V

NO.

UNIT

MIN

MAX

MIN

MAX

td (COH–TIN/TOUTH)

Delay time, CLKOUT high to TIN/TOUT high

-1

td (COH–TIN/TOUTL)

Delay time, CLKOUT high to TIN/TOUT low

-1

tw (TIN/TOUT)

Pulse duration, TIN/TOUT (output)

P - 1

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.

(2)

Only the Timer0 signal is externally available. The Timer1 signal is internally terminated and is not available for external use.

(3)

For proper operation of the TIN/TOUT pin configured as an output, the timer period must be configured for at least 4 cycles.

Figure 5-22. TIN/TOUT Timings When Configured as Inputs

Figure 5-23. TIN/TOUT Timings When Configured as Outputs

Electrical Specifications

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