TMS320VC5507 datasheet(42/108 Pages) TI1

42 / 108 page

SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

www.ti.com

3.11 Peripheral Register Description

Each 5507 device has a set of memory-mapped registers associated with peripherals as listed in

Table 3-20 through Table 3-35. Some registers use less than 16 bits. When reading these registers,

unused bits are always read as 0.

NOTE

The CPU access latency to the peripheral memory-mapped registers is 6 CPU cycles.

Following peripheral register update(s), the CPU must wait at least 6 CPU cycles before

attempting to use that peripheral. When more than one peripheral register is updated in a

sequence, the CPU only needs to wait following the final register write. For example, if the

EMIF is being reconfigured, the CPU must wait until the very last EMIF register update

takes effect before trying to access the external memory. The users should consult the

respective peripheral user’s guide to determine if a peripheral requires additional time to

initialize itself to the new configuration after the register updates take effect.

Before reading or writing to the USB register, the USB module has to be brought out of reset by setting bit

2 of the USB Idle Control and Status Register.

Table 3-20. Idle Control, Status, and System Registers

WORD ADDRESS

DESCRIPTION

RESET VALUE (1)

0x0001

ICR[7:0]

Idle control register

xxxx xxxx 0000 0100

0x0002

ISTR[7:0]

Idle status register

xxxx xxxx 0000 0000

0x07FD

SYSR[15:0]

System register

0000 0000 0000 0000

(1)

Hardware reset; x denotes a “don’t care'.

Table 3-21. External Memory Interface Registers

WORD ADDRESS

DESCRIPTION

RESET VALUE (1)

0x0800

EGCR[15:0]

EMIF global control register

xxxx xxxx 0010 xx00

0x0801

EMI_RST

EMIF global reset register

xxxx xxxx xxxx xxxx

0x0802

EMI_BE[13:0]

EMIF bus error status register

xx00 0000 0000 0000

0x0803

CE0_1[14:0]

EMIF CE0 space control register 1

x010 1111 1111 1111

0x0804

CE0_2[15:0]

EMIF CE0 space control register 2

0100 1111 1111 1111

0x0805

CE0_3[7:0]

EMIF CE0 space control register 3

xxxx xxxx 0000 0000

0x0806

CE1_1[14:0]

EMIF CE1 space control register 1

x010 1111 1111 1111

0x0807

CE1_2[15:0]

EMIF CE1 space control register 2

0100 1111 1111 1111

0x0808

CE1_3[7:0]

EMIF CE1 space control register 3

xxxx xxxx 0000 0000

0x0809

CE2_1[14:0]

EMIF CE2 space control register 1

x010 1111 1111 1111

0x080A

CE2_2[15:0]

EMIF CE2 space control register 2

0101 1111 1111 1111

0x080B

CE2_3[7:0]

EMIF CE2 space control register 3

xxxx xxxx 0000 0000

0x080C

CE3_1[14:0]

EMIF CE3 space control register 1

x010 1111 1111 1111

0x080D

CE3_2[15:0]

EMIF CE3 space control register 2

0101 1111 1111 1111

0x080E

CE3_3[7:0]

EMIF CE3 space control register 3

xxxx xxxx 0000 0000

0x080F

SDC1[15:0]

EMIF SDRAM control register 1

1111 1001 0100 1000

0x0810

SDPER[11:0]

EMIF SDRAM period register

xxxx 0000 1000 0000

0x0811

SDCNT[11:0]

EMIF SDRAM counter register

xxxx 0000 1000 0000

0x0812

INIT

EMIF SDRAM init register

xxxx xxxx xxxx xxxx

0x0813

SDC2[9:0]

EMIF SDRAM control register 2

xxxx xx11 1111 1111

0x0814

SDC3

EMIF SDRAM control register 3

0000 0000 0000 0111

(1)

Hardware reset; x denotes a “don’t care.”

Functional Overview

Submit Documentation Feedback

Product Folder Link(s): SM320VC5507-EP

TMS320VC5507 датащи(PDF) 42 Page - Texas Instruments

TMS320VC5507 датащи(HTML) 42 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL