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TMS320VC5507 датащи(PDF) 89 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 89 Page - Texas Instruments |
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89 / 108 page ![]() MC2, MC12 MC2, MC11 MC1 MC3 MC4 MC14 MC14 MC9 MC10 MC19 MC18 MC16 MC16 MC16 MC17 MC15 MC17 Bit 0 Bit (n1) (n2) (n3) (n4) Bit 0 Bit 0 Bit (n1) (n2) (n3) Bit (n1) (n2) CLKX FSX (Int) FSX (Ext) DX (XDATDLY=00b) DX (XDATDLY=01b) DX (XDATDLY=10b) SM320VC5507-EP www.ti.com SPRS613 – SEPTEMBER 2009 Figure 5-25. McBSP Transmit Timings 5.14.3 McBSP as SPI Master or Slave Timings Table 5-27 to Table 5-34 assume testing over recommended operating conditions (see Figure 5-26 through Figure 5-29). Table 5-27. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)(1) (2) CVDD = 1.2 V CVDD = 1.6 V CVDD = 1.35 V NO. UNIT MASTER SLAVE MASTER SLAVE MIN MAX MIN MAX MIN MAX MIN MAX MC23 tsu (DRV–CKXL) Setup time, DR valid before CLKX low 15 3 - 6P 10 3 - 6P ns MC24 th (CKXL–DRV) Hold time, DR valid after CLKX low 0 3 + 6P 0 3 + 6P ns Setup time, FSX low before CLKX MC25 tsu (FXL–CKXH) 5 5 ns high MC26 tc (CKX) Cycle time, CLKX 2P 16P 2P 16P ns (1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. (2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns. Copyright © 2009, Texas Instruments Incorporated Electrical Specifications 89 Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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