TMS320VC5507 datasheet(38/108 Pages) TI1

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USB

APLL

DPLL

USB

USB Module Clock

(48.0 MHz)

PLLSEL

CLKIN

Reserved

DPLLSTAT

APLLSTAT

PLLSEL

R, 0000 0000 0000 0

R, 1

R, 0

R/W, 0

LEGEND: R = Read, W = Write, n = value after reset

MULT

DIV

COUNT

MODE

STAT

R/W, 0000

R/W, 0

R, 0000 0000

R/W, 0

R, 0

LEGEND: R = Read, W = Write, n = value after reset

SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

www.ti.com

3.9

USB Clock Generation

The USB module can be clocked from either an Analog Phase-Locked Loop (APLL) or a Digital

Phase-Locked Loop (DPLL). The APLL is the recommended USB clock source due to better noise

tolerance and less long-term jitter than the DPLL. To maintain the backward compatibility, the DPLL is the

power-up default clock source for the USB module.

Figure 3-16. USB Clock Generation

Figure 3-17. USB PLL Selection and Status Register Bit Layout

Table 3-16. USB PLL Selection and Status Register Bit Functions

RESET

BIT NO.

BIT NAME

FUNCTION

VALUE

−3

Reserved

Reserved bits. Always write 0.

Status bit indicating if the DPLL is the source for the USB module clock.

DPLLSTAT

DPLLSTAT = 0;

The DPLL is not the USB module clock source.

DPLLSTAT = 1;

The DPLL is the USB module clock source.

Status bit indicating if the APLL is the source for the USB module clock.

APLLSTAT

APLLSTAT = 0;

The APLL is not the USB module clock source.

APLLSTAT = 1;

The APLL is the USB module clock source.

USB module clock source selection bit.

PLLSEL

PLLSEL = 0;

DPLL is selected as USB module clock source.

PLLSEL = 1;

APLL is selected as USB module clock source.

Figure 3-18. USB APLL Clock Mode Register Bit Layout

Functional Overview

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