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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5507 датащи(PDF) 101 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 101 Page - Texas Instruments |
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101 / 108 page  SM320VC5507-EP www.ti.com SPRS613 – SEPTEMBER 2009 5.16 I 2C Timings Table 5-39 and Table 5-39 assume testing over recommended operating conditions (see Figure 5-37 and Figure 5-38). Table 5-39. I2C Signals (SDA and SCL) Timing Requirements CVDD = 1.2 V CVDD = 1.6 V CVDD = 1.35 V NO. STANDARD FAST STANDARD FAST UNIT MODE MODE MODE MODE MIN MAX MIN MAX MIN MAX MIN MAX IC1 tc (SCL) Cycle time, SCL 10 2.5 10 2.5 μs Setup time, SCL high before SDA low for a IC2 tsu (SCLH–SDAL) 4.7 0.6 4.7 0.6 μs repeated START condition Hold time, SCL low after SDA low for a IC3 th (SCLL–SDAL) START and a 4 0.6 4 0.6 μs repeated START condition Pulse duration, SCL IC4 tw (SCLL) 4.7 1.3 4.7 1.3 μs low Pulse duration, SCL IC5 tw (SCLH) 4 0.6 4 0.6 μs high Setup time, SDA valid IC6 tsu (SDA–SCLH) 250 100(1) 250 100(1) ns before SCL high Hold time, SDA valid IC7 th (SDA–SCLL) 0(2) 0(2) 0.9(3) 0(2) 0(2) 0.9(3) μs after SCL low Pulse duration, SDA high between STOP IC8 tw (SDAH) 4.7 1.3 4.7 1.3 μs and START conditions 20 + 20 + IC9 tr (SDA) Rise time, SDA 1000 300 1000 0.1Cb 300 ns 0.1Cb (4) (4) 20 + 20 + IC10 tr (SCL) Rise time, SCL 1000 300 1000 0.1Cb 300 ns 0.1Cb (4) (4) 20 + 20 + IC11 tf (SDA) Fall time, SDA 300 300 300 0.1Cb 300 ns 0.1Cb (4) (4) 20 + 20 + IC12 tf (SCL) Fall time, SCL 300 300 300 0.1Cb 300 ns 0.1Cb (4) (4) Setup time, SCL high IC13 tsu (SCLH–SDAH) before SDA high (for 4 0.6 4 0.6 μs STOP condition) Pulse duration, spike IC14 tw (SP) 0 50 0 50 ns (must be suppressed) Capacitive load for IC15 Cb (4) 400 400 400 400 pF each bus line (1) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH) ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-Bus Specification) before the SCL line is released. (2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the undefined region of the falling edge of SCL. (3) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the LOW period [tw(SCLL)] of the SCL signal. (4) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed. Copyright © 2009, Texas Instruments Incorporated Electrical Specifications 101 Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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