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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5507 датащи(PDF) 28 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 28 Page - Texas Instruments |
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28 / 108 page  SM320VC5507-EP SPRS613 – SEPTEMBER 2009 www.ti.com Table 3-4. Synchronization Control Function SYNC FIELD IN SYNCHRONIZATION MODE DMA_CCR 00000b No event synchronized 00001b McBSP 0 receive event (REVT0) 00010b McBSP 0 transmit event (XEVT0) 00011b Reserved. These bits should always be written with 0. 00100b Reserved. These bits should always be written with 0. 00101b McBSP1 receive event (REVT1) 00110b McBSP1 transmit event (XEVT1) 00111b Reserved. These bits should always be written with 0. 01000b Reserved. These bits should always be written with 0. 01001b McBSP2 receive event (REVT2) 01010b McBSP2 transmit event (XEVT2) 01011b Reserved. These bits should always be written with 0. 01100b Reserved. These bits should always be written with 0. 01101b Timer 0 interrupt event 01110b Timer 1 interrupt event 01111b External interrupt 0 10000b External interrupt 1 10001b External interrupt 2 10010b External interrupt 3 10011b External interrupt 4 / I2C receive event (REVTI2C)(1) 10100b I2C transmit event (XEVTI2C) Other values Reserved (do not use these values) (1) The I2C receive event (REVTI2C) and external interrupt 4 (INT4) share a synchronization input to the DMA. When the SYNC field of the DMA_CCR is set to 10011b, the logical OR of these two sources is used for DMA synchronization. 3.5 I 2C Interface The SM320VC5507 includes an I2C serial port. The I2C port supports: • Compatibility with Philips I2C Specification Revision 2.1 (January 2000) • Operation at 100 Kbps or 400 Kbps • 7-bit addressing mode • Master (transmit/receive) and slave (transmit/receive) modes of operation • Events: DMA, interrupt, or polling The I2C module clock must be in the range from 7 MHz to 12 MHz. This is necessary for proper operation of the I2C module. With the I2C module clock in this range, the noise filters on the SDA and SCL pins suppress noise that has a duration of 50 ns or shorter. The I2C module clock is derived from the DSP clock divided by a programmable prescaler. NOTE I/O buffers are not fail-safe. The SDA and SCL pins could potentially draw current if the device is powered down and SDA and SCL are driven by other devices connected to the I 2C bus. 3.6 Configurable External Buses The 5507 offers combinations of configurations for its external parallel port. This allows the system designer to choose the appropriate media interface for its application without the need of a large-pin-count package. The External Bus Selection Register controls the routing of the parallel port signals. 28 Functional Overview Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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