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TMS320VC5507 датащи(PDF) 49 Page - Texas Instruments

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номер детали TMS320VC5507
подробное описание детали  Fixed-Point Digital Signal Processor
PDF  108 Pages
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производитель  TI1 [Texas Instruments]
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TMS320VC5507 датащи(HTML) 49 Page - Texas Instruments

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SM320VC5507-EP
www.ti.com
SPRS613 – SEPTEMBER 2009
Table 3-28. Multichannel Serial Port #2 (continued)
Transmit channel enable register partition B,
0x3011
XCERB_2[15:0]
0000 0000 0000 0000
McBSP #2
0x3012
PCR2[15:0]
Pin control register, McBSP #2
0000 0000 0000 0000
Receive channel enable register partition C,
0x3013
RCERC_2[15:0]
0000 0000 0000 0000
McBSP #2
Receive channel enable register partition D,
0x3014
RCERD_2[15:0]
0000 0000 0000 0000
McBSP #2
Transmit channel enable register partition C,
0x3015
XCERC_2[15:0]
0000 0000 0000 0000
McBSP #2
Transmit channel enable register partition D,
0x3016
XCERD_2[15:0]
0000 0000 0000 0000
McBSP #2
Receive channel enable register partition E,
0x3017
RCERE_2[15:0]
0000 0000 0000 0000
McBSP #2
Receive channel enable register partition F,
0x3018
RCERF_2[15:0]
0000 0000 0000 0000
McBSP #2
Transmit channel enable register partition E,
0x3019
XCERE_2[15:0]
0000 0000 0000 0000
McBSP #2
Transmit channel enable register partition F,
0x301A
XCERF_2[15:0]
0000 0000 0000 0000
McBSP #2
Receive channel enable register partition G,
0x301B
RCERG_2[15:0]
0000 0000 0000 0000
McBSP #2
Receive channel enable register partition H,
0x301C
RCERH_2[15:0]
0000 0000 0000 0000
McBSP #2
Transmit channel enable register partition G,
0x301D
XCERG_2[15:0]
0000 0000 0000 0000
McBSP #2
Transmit channel enable register partition H,
0x301E
XCERH_2[15:0]
0000 0000 0000 0000
McBSP #2
Table 3-29. GPIO
WORD ADDRESS
REGISTER NAME
PIN
DESCRIPTION
RESET VALUE(1)
0x3400
IODIR[7:0]
GPIO[7:0]
General–purpose I/O direction register
0000 0000 0000 0000
0x3401
IODATA[7:0]
GPIO[7:0]
General–purpose I/O data register
0000 0000 xxxx xxxx
0x4400
AGPIOEN[15:0]
A[15:0]
Address/GPIO enable register
0000 0000 0000 0000
0x4401
AGPIODIR[15:0]
A[15:0]
Address/GPIO direction register
0000 0000 0000 0000
0x4402
AGPIODATA[15:0]
A[15:0]
Address/GPIO data register
xxxx xxxx xxxx xxxx
0x4403
EHPIGPIOEN[5:0]
GPIO[13:8]
EHPI/GPIO enable register
0000 0000 0000 0000
0x4404
EHPIGPIODIR[5:0]
GPIO[13:8]
EHPI/GPIO direction register
0000 0000 0000 0000
0x4405
EHPIGPIODATA[5:0]
GPIO[13:8]
EHPI/GPIO data register
0000 0000 00xx xxxx
(1)
Hardware reset; x denotes a “don’t care.”
Table 3-30. Device Revision ID
WORD ADDRESS
REGISTER NAME
DESCRIPTION
VALUE (1)
Rev. 1.0:
0x3803
Rev ID[4:1]
Silicon revision identification
xxxx xxxx xxx0 001x
(1)
x denotes a “don’t care.”
Table 3-31. I2C Module Registers(1)
WORD ADDRESS
REGISTER NAME
DESCRIPTION
RESET VALUE(2)
(1)
I2C protocol compatible, no fail-safe buffer.
(2)
Hardware reset; x denotes a “don’t care.”
Copyright © 2009, Texas Instruments Incorporated
Functional Overview
49
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