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TMS320VC5507 датащи(PDF) 74 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 74 Page - Texas Instruments |
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74 / 108 page ![]() WRITE WRITE WRITE M22 M24 M26 M30 M34 M28 M32 M25 M27 M31 M23 M35 M29 M33 BE1 BE2 BE3 CA1 CA2 CA3 D1 D2 D3 CLKMEM CEx† BEx ‡ EMIF.A[13:0] D[15:0] SDA10 SDRAS SDCAS SDWE † The chip enable that becomes active depends on the address being accessed. ‡ All BE[1:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals r emain active until the next access that is not an SDRAM read occurs. SM320VC5507-EP SPRS613 – SEPTEMBER 2009 www.ti.com Figure 5-9. Three SDRAM WRT Commands 74 Electrical Specifications Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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