TMS320VC5507 datasheet(18/108 Pages) TI1

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SM320VC5507-EP

SPRS613 – SEPTEMBER 2009

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Table 2-2. Signal Descriptions (continued)

TERMINAL

MULTIPLEXED

RESET

I/O/Z (1)

FUNCTION

BK (2)

NAME

SIGNAL NAME

CONDITION

SDRAM A10 address line or general-purpose

IO13. This pin serves in one of two functions:

SDRAM A10 address line (EMIF.SDA10) or

C13

I/O/Z

general-purpose IO13 (GPIO13). The initial state

GPIO0 = 1:

of this pin depends on the GPIO0 pin. See

Section 3.6.1 for more information.

Output,

SDRAM A10 address line. Address

EMIF.SDA10

line/autoprecharge disable for SDRAM memory.

Serves as a row address bit (logically equivalent

to A12) during ACTV commands and also disables

GPIO0 = 0:

EMIF.SDA10

O/Z

the autoprecharging function of SDRAM during

read or write operations. EMIF.SDA10 is selected

Input,

when the Parallel Port Mode bit field of the

GPIO13

External Bus Selection Register is set to 00 or 01.

General-purpose IO13. GPIO13 is selected when

GPIO13

I/O/Z

the Parallel Port Mode bit field is set to 10 or 11.

Memory interface clock for SDRAM, HPI Data

Strobe 2 input, or general-purpose IO14. This pin

serves in one of two functions: memory interface

GPIO0 = 1:

C14

I/O/Z

clock for SDRAM (EMIF.CLKMEM) or HPI data

strobe 2 (HPI.HDS2). The initial state of this pin

Output,

depends on the GPIO0 pin. See Section 3.6.1 for

EMIF.CLKMEM

more information.

Memory interface clock for SDRAM.

EMIF.CLKMEM is selected when the Parallel Port

EMIF.CLKMEM

O/Z

GPIO0 = 0:

Mode bit field of the External Bus Selection

Input,

HPI Data Strobe 2 Input. HPI.HDS2 is driven by

HPI.HDS2

the host read or write strobes to control the

HPI.HDS2

transfer. HPI.HDS2 is selected when the Parallel

Port Mode bit field is set to 10 or 11.

INTERRUPT AND RESET PINS

Active-low external user interrupt inputs. INT[4:0]

INT[4:0]

are maskable and are prioritized by the interrupt

H, FS

Input

enable register (IER) and the interrupt mode bit.

Active-low reset. RESET causes the digital signal

processor (DSP) to terminate execution and

forces the program counter to FF8000h. When

RESET

RESET is brought to a high level, execution

H, FS

Input

begins at location FF8000h of program memory.

RESET affects various registers and status bits.

Use an external pullup resistor on this pin.

BIT I/O SIGNALS

7-bit Input/Output lines that can be individually

configured as inputs or outputs, and also

individually set or reset when configured as

GPIO[7:6, 4:0]

I/O/Z

Input

outputs. At reset, these pins are configured as

(GPIO5

inputs. After reset, the on-chip bootloader samples

only)

GPIO[3:0] to determine the boot mode selected.

SDRAM CKE signal. The GPIO4 pin can be

(except

configured to serve as SDRAM CKE pin by setting

GPIO5)

EMIF.CKE

Input

O/Z

the following bits in the External Bus Selection

(GPIO4)

default mode, this pin serves as GPIO4.

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