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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TMS320VC5507 датащи(PDF) 92 Page - Texas Instruments |
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TMS320VC5507 датащи(HTML) 92 Page - Texas Instruments |
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92 / 108 page  LSB MC36 MC37 MC38 MC26 MC31 MC39 MC35 MC33 MC34 MSB CLKX FSX DX DR Bit (n1) (n2) (n3) (n4) Bit 0 Bit 0 Bit (n1) (n2) (n3) (n4) MC32 SM320VC5507-EP SPRS613 – SEPTEMBER 2009 www.ti.com Table 5-31. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)(1) (2) CVDD = 1.2 V CVDD = 1.6 V CVDD = 1.35 V NO. MASTER SLAVE MASTER SLAVE UNIT MA MIN MAX MIN MIN MAX MIN MAX X MC33 tsu (DRV–CKXH) Setup time, DR valid before CLKX high 15 3 - 6P 10 3 - 6P ns MC34 th (CKXH–DRV) Hold time, DR valid after CLKX high 0 3 + 6P 0 3 + 6P ns MC36 tsu (FXL–CKXL) Setup time, FSX low before CLKX low 5 5 ns MC26 tc (CKX) Cycle time, CLKX 2P 16P 2P 16P ns (1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. (2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns. Table 5-32. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)(1) (2) CVDD = 1.2 V CVDD = 1.6 V CVDD = 1.35 V NO. UNIT MASTER (3) SLAVE MASTER (3) SLAVE MIN MAX MIN MAX MIN MAX MIN MAX Delay time, CLKX high to FSX MC37 td(CKXH–FXL) T - 5 T + 5 T - 4 T + 4 ns low(4) MC38 td(FXL–CKXL) Delay time, FSX low to CLKX low(5) D - 5 D + 5 D - 4 D + 4 ns MC35 td(CKXL–DXV) Delay time, CLKX low to DX valid -4 6 3P + 3 5P + 15 -3 3 3P + 3 5P + 8 ns Disable time, DX high–impedance MC39 tdis(CKXH–DXHZ) following last data bit from CLKX D - 4 D + 4 D - 3 D + 1 ns high Disable time, DX high–impedance MC31 tdis(FXH–DXHZ) 3P + 4 3P +19 3P + 3 3P +11 ns following last data bit from FSX high MC32 td(FXL–DXV) Delay time, FSX low to DX valid 3P + 4 3P + 18 3P + 4 3P + 10 ns (1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1. (2) P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns. (3) T = CLKX period = (1 + CLKGDV) * 2P C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even (4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on FSX and FSR is inverted before being used internally. CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP (5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (CLKX). Figure 5-28. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 92 Electrical Specifications Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SM320VC5507-EP |
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