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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8540 датащи(PDF) 142 Page - Freescale Semiconductor, Inc |
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MPC8540 датащи(HTML) 142 Page - Freescale Semiconductor, Inc |
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142 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 2-24 Freescale Semiconductor Memory Map PCI/X Error Management Registers 0x0_8E00 ERR_DR—PCI/X error detect register Special 0x0000_0000 16.3.1.4.1/16-29 0x0_8E04 ERR_CAP_DR—PCI/X error capture disabled register R/W 0x0000_0000 16.3.1.4.2/16-30 0x0_8E08 ERR_EN—PCI/X error enable register R/W 0x0000_0000 16.3.1.4.3/16-31 0x0_8E0C ERR_ATTRIB—PCI/X error attributes capture register R/W 0x0000_0000 16.3.1.4.4/16-32 0x0_8E10 ERR_ADDR—PCI/X error address capture register R/W 0x0000_0000 16.3.1.4.5/16-33 0x0_8E14 ERR_EXT_ADDR—PCI/X error extended address capture register R/W 0x0000_0000 16.3.1.4.6/16-34 0x0_8E18 ERR_DL—PCI/X error data low capture register R/W 0x0000_0000 16.3.1.4.7/16-34 0x0_8E1C ERR_DH—PCI/X error data high capture register R/W 0x0000_0000 16.3.1.4.8/16-34 0x0_8E20 GAS_TIMR—PCI/X gasket timer register R/W 0x0000_0000 16.3.1.4.9/16-35 0x0_8E24 PCIX_TIMR—PCIX split completion timer register R/W 0x0000_0000 16.3.1.4.10/16-36 0x0_8E28– 0x0_8EFC Reserved — — 0x0_8F00– 0x0_8FFC Reserved for debug — — L2/SRAM Memory-Mapped Configuration Registers 0x2_0000 L2CTL—L2 control register R/W 0x2000_0000 7.3.1.1/7-7 0x2_0010 L2CEWAR0—L2 cache external write address register 0 R/W 0x0000_0000 7.3.1.2/7-10 0x2_0018 L2CEWCR0—L2 cache external write control register 0 R/W 0x0000_0000 7.3.1.3/7-10 0x2_0020 L2CEWAR1—L2 cache external write address register 1 R/W 0x0000_0000 7.3.1.2/7-10 0x2_0028 L2CEWCR1—L2 cache external write control register 1 R/W 0x0000_0000 7.3.1.3/7-10 0x2_0030 L2CEWAR2—L2 cache external write address register 2 R/W 0x0000_0000 7.3.1.2/7-10 0x2_0038 L2CEWCR2—L2 cache external write control register 2 R/W 0x0000_0000 7.3.1.3/7-10 0x2_0040 L2CEWAR3—L2 cache external write address register 3 R/W 0x0000_0000 7.3.1.2/7-10 0x2_0048 L2CEWCR3—L2 cache external write control register 3 R/W 0x0000_0000 7.3.1.3/7-10 0x2_0100 L2SRBAR0—L2 memory-mapped SRAM base address register 0 R/W 0x0000_0000 7.3.1.4/7-11 0x2_0108 L2SRBAR1—L2 memory-mapped SRAM base address register 1 R/W 0x0000_0000 7.3.1.4/7-11 Table 2-9. Memory Map (continued) Offset Register Access Reset Section/Page |
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