MPC8540 datasheet(30/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

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Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

16.3.2.2

PCI Device ID Register—Offset 0x02 ................................................................ 16-38

16.3.2.3

PCI Bus Command Register—Offset 0x04 ......................................................... 16-38

16.3.2.4

PCI Bus Status Register—Offset 0x06................................................................ 16-40

16.3.2.5

PCI Revision ID Register—Offset 0x08 ............................................................. 16-41

16.3.2.6

PCI Bus Programming Interface Register—Offset 0x09 .................................... 16-41

16.3.2.7

PCI Subclass Code Register—Offset 0x0A......................................................... 16-42

16.3.2.8

PCI Bus Base Class Code Register—Offset 0x0B .............................................. 16-42

16.3.2.9

PCI Bus Cache Line Size Register—Offset 0x0C............................................... 16-43

16.3.2.10

PCI Bus Latency Timer Register—0x0D ............................................................ 16-43

16.3.2.11

PCI Base Address Registers ................................................................................ 16-43

16.3.2.12

PCI Subsystem Vendor ID Register..................................................................... 16-46

16.3.2.13

PCI Subsystem ID Register ................................................................................. 16-46

16.3.2.14

PCI Bus Capabilities Pointer Register ................................................................. 16-47

16.3.2.15

PCI Bus Interrupt Line Register .......................................................................... 16-47

16.3.2.16

PCI Bus Interrupt Pin Register ............................................................................ 16-48

16.3.2.17

PCI Bus Minimum Grant (MIN_GNT) Register................................................. 16-48

16.3.2.18

PCI Bus Maximum Latency (MAX_LAT) Register............................................ 16-49

16.3.2.19

PCI Bus Function Register (PBFR) ..................................................................... 16-49

16.3.2.20

PCI Bus Arbiter Configuration Register (PBACR)............................................. 16-50

16.3.2.21

PCI-X Next Capabilities ID Register—0x60 ...................................................... 16-51

16.3.2.22

PCI-X Capability Pointer Register—0x61 .......................................................... 16-51

16.3.2.23

PCI-X Command Register—0x62 ....................................................................... 16-52

16.3.2.24

PCI-X Status Register—0x64.............................................................................. 16-52

16.4

Functional Description................................................................................................. 16-53

16.4.1

PCI/X Bus Arbitration ............................................................................................. 16-53

16.4.1.1

PCI/X Bus Arbiter Operation .............................................................................. 16-54

16.4.1.2

PCI/X Bus Parking .............................................................................................. 16-56

16.4.1.3

Broken Master Lock-Out (PCI only) ................................................................... 16-56

16.4.1.4

Power-Saving Modes and the PCI Arbiter .......................................................... 16-56

16.4.2

PCI Bus Protocol ..................................................................................................... 16-56

16.4.2.1

Basic Transfer Control......................................................................................... 16-57

16.4.2.2

PCI Bus Commands............................................................................................. 16-57

16.4.2.3

Addressing ........................................................................................................... 16-59

16.4.2.3.1

Memory Space Addressing.............................................................................. 16-59

16.4.2.3.2

I/O Space Addressing ...................................................................................... 16-60

16.4.2.3.3

Configuration Space Addressing ..................................................................... 16-60

16.4.2.4

Device Selection .................................................................................................. 16-60

16.4.2.5

Byte Alignment.................................................................................................... 16-61

16.4.2.6

Bus Driving and Turnaround ............................................................................... 16-61

16.4.2.7

PCI Bus Transactions........................................................................................... 16-61

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