MPC8540 datasheet(47/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

xlvii

Figures

Figure

Number

Title

Page

Number

9-29

DDR SDRAM Clock Distribution Example ......................................................................... 9-38

9-30

DDR SDRAM Mode-Set Command Timing ........................................................................ 9-39

9-31

Registered DDR SDRAM DIMM Burst Write Timing ........................................................ 9-40

9-32

Write Timing Adjustments Example..................................................................................... 9-41

9-33

DDR SDRAM Bank-Staggered Auto-Refresh Timing ......................................................... 9-42

9-34

DDR SDRAM Power-Down Mode ...................................................................................... 9-43

9-35

DDR SDRAM Self-Refresh Entry Timing ........................................................................... 9-44

9-36

DDR SDRAM Self-Refresh Exit Timing ............................................................................. 9-44

10-1

MPC8540 Interrupt Sources Block Diagram ........................................................................ 10-3

10-2

Pass-Through Mode Example ............................................................................................... 10-6

10-3

Feature Reporting Register (FRR) ...................................................................................... 10-16

10-4

Global Configuration Register (GCR) ................................................................................ 10-17

10-5

Vendor Identification Register (VIR).................................................................................. 10-17

10-6

Processor Initialization Register (PIR) ............................................................................... 10-18

10-7

IPI Vector/Priority Registers (IPIVPRn)............................................................................. 10-19

10-8

Spurious Vector Register (SVR) ......................................................................................... 10-20

10-9

Timer Frequency Reporting Register (TFRR) .................................................................... 10-20

10-10

Global Timer Current Count Registers (GTCCRn) ............................................................ 10-21

10-11

Global Timer Base Count Registers (GTBCRn)................................................................. 10-22

10-12

Global Timer Vector/Priority Registers (GTVPRn)............................................................ 10-22

10-13

Global Timer Destination Registers (GTDRn) ................................................................... 10-23

10-14

Example Calculation for Cascaded Timers ......................................................................... 10-24

10-15

Timer Control Register (TCR) ............................................................................................ 10-24

10-16

IRQ_OUT Summary Register 0 (IRQSR0) ........................................................................ 10-26

10-17

IRQ_OUT Summary Register 1 (IRQSR1) ........................................................................ 10-27

10-18

Critical Interrupt Summary Register 0 (CISR0) ................................................................. 10-27

10-19

Critical Interrupt Summary Register 1 (CISR1) ................................................................. 10-28

10-20

Performance Monitor Mask Registers (PMnMR0)............................................................. 10-29

10-21

Performance Monitor Mask Registers (PMnMR1)............................................................. 10-30

10-22

Message Registers (MSGRs) .............................................................................................. 10-30

10-23

Message Enable Register (MER) ........................................................................................ 10-31

10-24

Message Status Register (MSR) ......................................................................................... 10-31

10-25

External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ..................................... 10-32

10-26

External Interrupt Destination Registers (EIDRn).............................................................. 10-33

10-27

Internal Interrupt Vector/Priority Registers (IIVPRn) ........................................................ 10-34

10-28

Internal Interrupt Destination Registers (IIDRn) ................................................................ 10-35

10-29

Messaging Interrupt Vector/Priority Registers (MIVPRn) ................................................. 10-36

10-30

Messaging Interrupt Destination Registers (MIDRn) ......................................................... 10-37

10-31

Per-CPU Register Address Decoding in a Four-Core Device............................................. 10-39

10-32

Interprocessor Interrupt Dispatch Registers (IPIDR0–IPIDR3) ......................................... 10-39

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