MPC8540 datasheet(12/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

xii

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

Chapter 7

L2 Look-Aside Cache/SRAM

7.1

L2 Cache Overview ......................................................................................................... 7-1

7.1.1

L2 Cache and SRAM Features .................................................................................... 7-2

7.2

Cache Organization.......................................................................................................... 7-3

7.3

Memory Map/Register Definition ................................................................................... 7-6

7.3.1

L2/SRAM Register Descriptions ................................................................................. 7-7

7.3.1.1

L2 Control Register (L2CTL).................................................................................. 7-7

7.3.1.2

L2 Cache External Write Address Registers 0–3 (L2CEWARn) .......................... 7-10

7.3.1.3

L2 Cache External Write Control Registers 0–3 (L2CEWCRn) ........................... 7-10

7.3.1.4

L2 Memory-Mapped SRAM Base Address Registers 0–1

(L2SRBARn) ..................................................................................................... 7-11

7.3.1.5

L2 Error Registers.................................................................................................. 7-12

7.3.1.5.1

Error Injection Registers.................................................................................... 7-13

7.3.1.5.2

Error Control and Capture Registers ................................................................. 7-15

7.4

External Writes to the L2 Cache (Cache Stashing)........................................................ 7-21

7.5

L2 Cache Timing ........................................................................................................... 7-21

7.6

L2 Cache and SRAM Coherency................................................................................... 7-22

7.6.1

L2 Cache Coherency Rules........................................................................................ 7-22

7.6.2

Memory-Mapped SRAM Coherency Rules .............................................................. 7-24

7.7

L2 Cache Locking.......................................................................................................... 7-24

7.7.1

Locking the Entire L2 Cache ..................................................................................... 7-25

7.7.2

Locking Programmed Memory Ranges ..................................................................... 7-25

7.7.3

Locking Selected Lines.............................................................................................. 7-25

7.7.4

Clearing Locks on Selected Lines ............................................................................. 7-26

7.7.5

Flash Clearing of Instruction and Data Locks ........................................................... 7-27

7.7.6

Locks with Stale Data ................................................................................................ 7-27

7.8

PLRU L2 Replacement Policy....................................................................................... 7-27

7.8.1

PLRU Bit Update Considerations.............................................................................. 7-28

7.8.2

Allocation of Lines .................................................................................................... 7-29

7.9

L2 Cache Operation ....................................................................................................... 7-29

7.9.1

L2 Cache States ......................................................................................................... 7-29

7.9.2

Flash Invalidation of the L2 Cache............................................................................ 7-30

7.9.3

L2 State Transitions ................................................................................................... 7-30

7.10

Initialization/Application Information ........................................................................... 7-34

7.10.1

Initialization ............................................................................................................... 7-35

7.10.1.1

L2 Cache Initialization .......................................................................................... 7-35

7.10.1.2

Memory-Mapped SRAM Initialization ................................................................. 7-35

7.10.2

Managing Errors ........................................................................................................ 7-35

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