MPC8540 datasheet(58/1302 Pages) FREESCALE

58 / 1302 page

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

lviii

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

17-38

RapidIO Inbound Window Attributes Registers 1–4 (RIWARn)........................................ 17-42

17-39

Port Notification/Fatal Error Detect Register (PNFEDR) .................................................. 17-44

17-40

Port Notification/Fatal Error Detect Disable Register (PNFEDiR) .................................... 17-47

17-41

Port Notification/Fatal Error Interrupt Enable Register (PNFEIER).................................. 17-49

17-42

Port Error Capture Status Register (PECSR) ...................................................................... 17-52

17-43

Error Packet Capture Register 0 (EPCR0) .......................................................................... 17-52

17-44

Error Packet Capture Register 1 (EPCR1)—Type 1 Packet Format................................... 17-53

17-45

Error Packet Capture Register 1 (EPCR1)—Type 2 Packet Format................................... 17-54

17-46

Error Packet Capture Register 1 (EPCR1)—Type 5 Packet Format................................... 17-54

17-47

Error Packet Capture Register 1 (EPCR1)—Type 6 Packet Format................................... 17-55

17-48

Error Packet Capture Register 1 (EPCR1)—Type 8 Request Packet Format..................... 17-55

17-49

Error Packet Capture Register 1 (EPCR1)—Type 8 Response Packet Format .................. 17-56

17-50

Error Packet Capture Register 1 (EPCR1)—Type 10 Packet Format................................. 17-57

17-51

Error Packet Capture Register 1 (EPCR1)—Type 11 Packet Format ................................. 17-57

17-52

Error Packet Capture Register 1 (EPCR1)—Type 13 Packet Format................................. 17-58

17-53

Error Packet Capture Register 2 (EPCR2)—Type 1, 2, or 5 Packet Format ...................... 17-58

17-54

Error Packet Capture Register 2 (EPCR2)—Type 6 Packet Format................................... 17-59

17-55

Error Packet Capture Register 2 (EPCR2)—Type 8 Request Packet Format..................... 17-59

17-56

Error Packet Capture Register 2 (EPCR2)—Type 8 Response Packet Format .................. 17-60

17-57

Error Packet Capture Register 2 (EPCR2)—Type 10 Packet Format................................. 17-60

17-58

Error Packet Capture Register 2 (EPCR2)—Type 11 or 13 Packet Format........................ 17-61

17-59

Port Recoverable Error Detect Register (PREDR) ............................................................. 17-61

17-60

Port Error Recovery Threshold Register (PERTR)............................................................. 17-64

17-61

Port Retry Threshold Register (PRTR) ............................................................................... 17-64

17-62

Outbound Mode Register (OMR) ....................................................................................... 17-65

17-63

Outbound Status Register (OSR) ........................................................................................ 17-67

17-64

Outbound Descriptor Queue Dequeue Pointer Address Register (ODQDPAR)................. 17-69

17-65

Outbound Unit Source Address Registers (OSAR) ............................................................ 17-69

17-66

Outbound Destination Port Registers (ODPR) ................................................................... 17-70

17-67

Outbound Destination Attributes Register (ODATR) ......................................................... 17-70

17-68

Outbound Double-Word Count Register (ODCR) .............................................................. 17-71

17-69

Outbound Descriptor Queue Enqueue Pointer Register (ODQEPAR) ............................... 17-72

17-70

Inbound Mode Register (IMR) ........................................................................................... 17-73

17-71

Inbound Status Register (ISR) ............................................................................................ 17-74

17-72

Inbound Frame Queue Dequeue Pointer Address Registers (IFQDPAR)........................... 17-75

17-73

Inbound Frame Queue Enqueue Pointer Address Registers (IFQEPAR) ........................... 17-76

17-74

Doorbell Mode Register (DMR) ......................................................................................... 17-77

17-75

Doorbell Status Register (DSR).......................................................................................... 17-78

17-76

Doorbell Queue Dequeue Pointer Address Registers (DQDPAR)...................................... 17-80

17-77

Doorbell Queue Enqueue Pointer Address Register (DQEPAR)........................................ 17-80

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